M+N bit programming and M+L bit read for M bit memory cells

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185210, C365S185240, C365S185110

Reexamination Certificate

active

07633798

ABSTRACT:
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.

REFERENCES:
patent: 5737265 (1998-04-01), Atwood et al.
patent: 7221592 (2007-05-01), Nazarian
patent: 2006/0004952 (2006-01-01), Lasser
patent: 2006/0285392 (2006-12-01), Incarnati et al.
patent: 2008/0062760 (2008-03-01), Kim

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