M+L bit read column architecture for M bit memory cells

Details M+L bit read column architecture for M bit memory cells M+L bit read column architecture for M bit memory cells

2008-06-11

2010-11-30

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185120, C365S185180, C365S189050

Reexamination Certificate

active

07843725

ABSTRACT:
A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program operation to minimize disturb within the pages of the row, while verifying each memory cell page of the row separately. In one embodiment of the present invention, the memory device utilizes data latches to program M-bits of data into each cell of the row and then repurposes the data latches during the subsequent page verify operations to read M+L bits from each cell of the selected page at a higher threshold voltage resolution than required. In sensing, the increased threshold voltage resolution/granularity allows interpretations of the actual programmed state of the memory cell and enables more effective use of data encoding and decoding techniques such as convolutional codes where additional granularity of information is used to make soft decisions reducing the overall memory error rate.

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