Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-09-21
2009-08-04
Do, Chat C (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07571204
ABSTRACT:
There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument, and generates a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the CX(0) bit is calculated assuming the row carry-out bit from the second row is a 0.
REFERENCES:
patent: 3553446 (1971-01-01), Kruy
patent: 4623982 (1986-11-01), Ware
patent: 4682303 (1987-07-01), Uya
patent: 5018093 (1991-05-01), Shih
patent: 5126965 (1992-06-01), Asato et al.
patent: 5163020 (1992-11-01), Chau
patent: 5181186 (1993-01-01), Al-Ofi
patent: 5204832 (1993-04-01), Nakakura
patent: 5272662 (1993-12-01), Scriber et al.
patent: 5396445 (1995-03-01), Lal
patent: 5499203 (1996-03-01), Grundland
patent: 5523963 (1996-06-01), Hsieh et al.
patent: 5579254 (1996-11-01), Kumar et al.
patent: 5732008 (1998-03-01), Abu-Khater et al.
patent: 5787492 (1998-07-01), Shuma et al.
patent: 5852568 (1998-12-01), Ranjan
patent: 5875125 (1999-02-01), Hwang et al.
patent: 0 352 549 (1990-01-01), None
patent: WO 98/51013 (1998-11-01), None
Akhilesh, A reduced-area scheme for carry-selected adders, 1993, IEEE transactions on computers, vol. 42, No. 10, pp. 1163-1170.
Abu-Khater et al., Circuit/Architecture for low-power high-performance 32 bit adder, 1995, IEEE, pp. 74-77.
Becker et al., A performance driven generator for efficient testable conditional sum adders, 1992, IEEE, pp. 370-375.
Cheng et al., The improvement of conditional sum adder for low power applications, 1998, IEEE, pp. 131-134.
Department of Electrical Engineering of Linkopings University, “Arithmetic Building Blocks”, Prentice Hall, 1995, pp. 1-21, retrieved from the internet: www.ek.isy.liu.se/course/tsek30/current/Arithm.pdf, on Jun. 1, 2006.
David A. Patterson et al., “Computer Architecture A Quantitative Approach”, 1990 Morgan Kaufmann Publishers, Inc., San Francisco, California, pp. A45-A46.
Do Chat C
Jorgenson Lisa K.
Munck William A.
STMicroelectronics Inc.
LandOfFree
M-bit race delay adder and method of operation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with M-bit race delay adder and method of operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and M-bit race delay adder and method of operation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4124469