M&A for dynamically generating and maintaining frame based polli

Details M&A for dynamically generating and maintaining frame based polli M&A for dynamically generating and maintaining frame based polli

1994-10-31

1998-04-21

Lee, Thomas C.

Multiplex communications

Wide area network

Packet switching

395836, 395861, 370 951, 370 952, G06F 1314, G06F 1320, G06F 1322

Patent

active

057428476

ABSTRACT:
Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

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