Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection
Reexamination Certificate
2001-01-22
2002-08-13
Jackson, Jr., Jerome (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Device protection
C257S358000, C257S141000, C257S357000
Reexamination Certificate
active
06433368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a low-voltage triggering silicon-controlled rectifier (LVTSCR) and, more particularly, to a LVTSCR with a holding voltage that is greater than a dc bias voltage on a to-be-protected node.
2. Description of the Related Art
A silicon-controlled rectifier (SCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a trigger voltage. When the voltage across the first and second nodes rises to be equal to or greater than the trigger voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the trigger voltage.
As a result of these characteristics, SCRs have been used to provide electro-static discharge (ESD) protection. When used for ESD protection, the first node becomes a to-be-protected node, and the second node becomes an output node. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias on the to-be-protected node. The trigger voltage of the SCR is then set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window.
Thus, when the voltage across the to-be-protected node and the output node is less than the trigger voltage, the SCR provides an open circuit between the to-be-protected node and the output node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body contact occurs, the SCR provides a low-resistance current path from the to-be-protected node to the output node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the output node.
FIG. 1
shows a cross-sectional view that illustrates a conventional SCR
100
. As shown in
FIG. 1
, SCR
100
has a n-well
112
which is formed in a p-type semiconductor material
110
, such as a substrate or a well, and a n+ region
114
and a p+ region
116
which are formed in n-well
112
. N+ and p+ regions
114
and
116
, in turn, are both connected to a to-be-protected node
120
. As further shown in
FIG. 1
, SCR
100
also has a n+ region
122
and a p+ region
124
formed in semiconductor material
110
. N+ and p+ regions
122
and
124
, in turn, are both connected to an output node
126
.
In operation, when the voltage across nodes
120
and
126
is positive and less than the trigger voltage, the voltage reverse biases the junction between n-well
112
and p-type material
110
. The reverse-biased junction, in turn, blocks charge carriers from flowing from node
120
to node
126
. However, when the voltage across nodes
120
and
126
is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into material
110
, and a large number of electrons to be injected into n-well
112
. The increased number of holes increases the potential of material
110
in the region that lies adjacent to n+ region
122
, and eventually forward biases the junction between material
110
and n+ region
122
.
When the increased potential forward biases the junction, a npn transistor that utilizes n+ region
122
as the emitter, p-type material
110
as the base, and n-well
112
as the collector turns on. When turned on, n+ (emitter) region
122
injects electrons into (base) material
110
. Most of the injected electrons diffuse through (base) material
110
and are swept from (base) material
110
into (collector) n-well
112
by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well
112
are then collected by n+ region
114
.
A small number of the electrons injected into (base) material
110
recombine with holes in (base) material
110
and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material
110
by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n-well
112
also decrease the potential of n-well
112
in the region that lies adjacent to p+ region
116
, and eventually forward bias the junction between p+ region
116
and n-well
112
. When the decreased potential forward biases the junction between p+ region
116
and n-well
112
, a pnp transistor formed from p+ region
116
, n-well
112
, and material
110
turns on.
When turned on, p+ emitter
116
injects holes into base
112
. Most of the injected holes diffuse through (base) n-well
112
and are swept from (base) n-well
112
into (collector) material
110
by the electric field that extends across the reverse-biased junction. The holes in (collector) material
110
are then collected by p+ region
124
.
A small number of the holes injected into (base) n-well
112
recombine with electrons in (base) n-well
112
and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well
112
as a result of the broken-down reverse-biased junction, and n-well
112
being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material
110
also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region
122
. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region
122
injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region
116
injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
One of the advantages of SCR
100
over other ESD protection devices, such as a grounded-gate MOS transistor, is the double injection provided by n+ region
122
and p+ region
116
of SCR
100
. With double injection, SCR
100
provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device, thus increasing the ESD protection capability. (Protection capability can be defined as the required contact width of the structure required to protect from a given ESD pulse amplitude, or the maximum protected ESD pulse amplitude for a given contact width.) One of the disadvantages of SCR
100
, however, is that a very large positive voltage, e.g., 50 volts, must be dropped across nodes
120
and
126
before the junction between p-type material
110
and n-well
112
breaks down. As a result, SCR
100
can not be used to protect devices, such as MOS transistors, that can be permanently damaged by much lower voltages, e.g., 15 volts.
One solution to this problem, known as a low-voltage triggering SCR (LVTSCR), incorporates a NMOS transistor into SCR
100
.
FIG. 2
shows a cross-sectional diagram that illustrates a conventional LVTSCR
200
. LVTSCR
200
and SCR
100
are similar and, as a result, utilize the same referenc
Hopper Peter J.
Vashchenko Vladislav
National Semiconductor Corporation
Pickering Mark C.
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