LSSD edge detection logic for asynchronous data interface

Details LSSD edge detection logic for asynchronous data interface LSSD edge detection logic for asynchronous data interface

1987-11-17

1990-10-09

Zache, Raulfe B.

Boots, shoes, and leggings

3649328, 36492792, 36492793, G06F 300

Patent

active

049624741

ABSTRACT:
An interface between a computer and an asynchronous communications line in which asynchronous data on the communications line sets a register made up of latches designed according to LSSD rules, which is then read out and reset in synchronism with the computer. The latches for each individual bit position of the register are edge triggered providing for maximum speed of transmission and are designed to be tested using LSSD test criteria. Data is frozen in the register upon receipt of a data valid signal. The contents of the register are then synchronously gated internally within the computer.

REFERENCES:
patent: 4100605 (1978-07-01), Holman
patent: 4225959 (1980-09-01), Doty, Jr. et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4362957 (1982-12-01), Stern
patent: 4477902 (1984-10-01), Puri et al.
patent: 4564943 (1986-01-01), Collins et al.

Affiliated with

Also associated with

Rating

LSSD edge detection logic for asynchronous data interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with LSSD edge detection logic for asynchronous data interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LSSD edge detection logic for asynchronous data interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-977024