LSSD Compatible clock driver

Details LSSD Compatible clock driver LSSD Compatible clock driver

1982-06-14

1984-10-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307582, 307269, 324 73R, H03K 513, G01R 3102

Patent

active

044777388

ABSTRACT:
A cross-coupled, latch-type clock driver circuit is disclosed which enables the carrying out of level sensitive scan design (LSSD) testing. During normal operation, the circuit functions to prevent a pair of input clock waveforms from overlapping. This is achieved by applying a low state to a control signal input which causes the circuit to perform a latching operation on the input clock waveforms by providing a conductive cross-coupled connection between a first and second NOR Logic elements connected to the input clock waveforms. Then the outputs of the NOR elements will be insured to be nonoverlapping. During the test mode, the input clock waveforms must not be latched, in order for LSSD testing to be carried out. This is achieved by applying a high state to the control signal input, which disables the cross-coupled connection between the NOR logic elements. The circuit then becomes transparent to the input clock waveforms, enabling testing operations to be performed. The transition of the circuit from its normal mode to its test mode is carried out with a staged delay operation to prevent inadvertent current surges.

REFERENCES:
patent: 3769525 (1973-10-01), Foss et al.
patent: 3815025 (1974-06-01), Jordan
patent: 3882390 (1975-05-01), Lucas
patent: 3965459 (1976-06-01), Spencer et al.
patent: 4035663 (1977-07-01), Stodola
patent: 4241307 (1980-12-01), Hong
patent: 4286173 (1981-08-01), Oka et al.
patent: 4315167 (1982-02-01), Pelc

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