LSI Timing circuit for a digital display employing a modulo eigh

Details LSI Timing circuit for a digital display employing a modulo eigh LSI Timing circuit for a digital display employing a modulo eigh

1980-11-10

1983-06-28

Britton, Howard

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

328187, 340744, 340804, 358150, 364521, 377 33, 377 43, 377 46, G06F 314, H03K 117, H03K 2136, H04N 506

Patent

active

043907806

ABSTRACT:
This disclosure relates to a timing circuit for a digital display, which circuit includes a series of counters, each having four stages such that each counter will drive the next stage only when it has progressed from zero to seven. By reading out the state of each stage of the respective counters, selected counts can be decoded from only two of the respective stage readouts.

REFERENCES:
patent: 3777063 (1973-12-01), Meacham
patent: 3816764 (1974-06-01), King
patent: 3896388 (1975-07-01), Hatsukano
patent: 3920901 (1975-11-01), Boehly
patent: 4119954 (1978-10-01), Seitz
patent: 4196431 (1980-04-01), Lee
IBM Technical Disclosure Bulletin, vol. 3, No. 1, Jun. 1960, pp. 25-27, L. R. Harper, "Folded Ring".

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