LSI self-test method

Details LSI self-test method LSI self-test method

1982-09-29

1985-05-21

Atkinson, Charles E.

Excavating

324 73AT, 324 73R, 371 27, G01R 3128

Patent

active

045190780

ABSTRACT:
A method of self-testing LSI circuits and/or systems in which LSI and discrete logic circuits are used that incorporates internally generated pseudorandom sequences as test vectors to stimulate the logic circuits under test. Responses to the test vectors are analyzed internally or externally using signature analysis to determine if the circuit has functioned properly. The method combines the best features of Level Sensitive Scan Design and prior art self-test methods to provide an efficient, easy to perform, self-test method that may be used at any testing level.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Baxter
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4435806 (1984-03-01), Segers et al.
patent: 4450560 (1984-05-01), Conner
patent: 4454600 (1984-06-01), LeGresley
Williams, T. W. et al, "A Logic Design Structure for Totability", Proc. 14th Design Automation Conference, Jun. 1977, pp. 462-468.

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