Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-06-17
2001-05-22
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C361S777000, C257S700000, C257S691000, C257S664000
Reexamination Certificate
active
06235997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an LSI package, and particularly relates to an LSI package including an LSI device operating at a higher clock frequency.
Recent LSI devices tend to operate at higher frequency and with higher electrical consumption. Accordingly, there is a need for packages for mounting the LSI devices thereon, or LSI packages, which can be used with such LSI devices. Thus, the LSI packages are modified as follows.
First, in order to stabilize an electric current supply, the LSI package is formed in a multilayer structure with an inner layer provided with a source/ground plane. Secondly, in order to reduce an inductance of source/ground lines, the source/ground lines are provided so as to be short in length and broad in width. Thirdly, in order to achieve a 50 &OHgr; impedance matching, gaps between layers are adjusted by providing planes on layers above and below wiring layers. Finally, in order to reduce mutual inductance and crosstalk, gaps between signal lines are widened so that the signal lines do not interfere with each other.
2. Description of the Related Art
Now an LSI package of the related art will be described in detail with reference to
FIGS. 1 and 2
. An LSI package
1
shown in
FIGS. 1 and 2
is a double-layer package including an upper layer
2
(shown in
FIG. 1
) and a lower layer
3
(shown in FIG.
2
).
FIGS. 1 and 2
show ⅛ of the whole pattern of the LSI package
1
.
As shown in
FIGS. 1 and 2
, through-hole lands
4
are formed in a matrix form on both the upper layer
2
and the lower layer
3
. The through-hole lands
4
are connected to external terminals via through-holes. The external terminals are provided with, for example, bumps. With the structure described above, the LSI package
1
may be used as a BGA (Ball Grid Array) type package.
Also, the upper layer
2
and the lower layer
3
are provided with a number of lines
5
. Each of the lines
5
is connected to one of the external terminals via a through-hole at one end, and to an electrode pad
6
on the other end. The electrode pads
6
are formed on the upper layer
2
and the lower layer
3
at positions facing a semiconductor chip (not shown). The electrode pads
6
are electrically connected to the semiconductor chip using wires.
Now, the lines
5
will be described in detail. In the related art, the relationship between the lengths of the lines
5
on either the upper layer
2
or the lower layer
3
, or the lines
5
on both the upper layer
2
and the lower layer
3
, was not of a great interest. The wiring pattern was determined so as to facilitate the forming process of the lines
5
.
However, for source lines and for ground/source lines, which are labeled a-g in
FIGS. 1 and 2
, the line lengths were shortened for the sake of electrical feature and the line widths were broadened as shown by the line labeled g in FIG.
2
. Also, impedance matching was achieved by a multilayer package provided with a signal-transmitting layer held between the source planar layer and the ground planer layer.
In the related art, improvement of electrical characteristics of the LSI package
1
has focused on improvement of the LCR characteristics or the 50 &OHgr; matching of the characteristic impedance according to the modifications described above. Thus, the LCR characteristics, the impedance matching of the LSI package, and crosstalk problems have been improved. However, there is still a need for reducing the noise produced by the mismatch of transmission times between differential signals.
Also, when the above-described modifications are applied to the recent LSI devices having a clock frequency of over 1 GHz, there is a problem that when the LSI device is mounted on the LSI package
1
, the LSI device (semiconductor device) does not operate.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an LSI package which can solve the problems described above.
It is another and more specific object of the present invention to provide an LSI package which can achieve an improvement in the electrical characteristics even when an LSI device, which uses a higher clock frequency, is mounted on the LSI package.
It is still another object of the present invention to provide an LSI package, which can reduce the transmission time lag between differential signals, thus reducing the noise and improving electrical characteristics.
In order to achieve the above objects, an LSI package includes:
an area for mounting an LSI device thereon; and
a plurality of lines for connecting the LSI device and external terminals,
wherein at least two of the plurality of lines, in which differential signals are transmitted and are adjacent to each other in the LSI package, have equal lengths.
Further, the LSI package includes a multilayer structure having layers provided with the plurality of lines thereon, wherein the lines having equal lengths are provided on one of the layers. Also, the LSI package may include a multilayer structure having layers provided with the plurality of lines thereon, wherein the lines having equal lengths are provided on different ones of the layers.
It is yet another object of the present invention to provide an LSI package which can reduce the transmission time lag between differential signals including any loss at wires, thus improving electrical characteristics.
In order to achieve the above object, the plurality of lines connected to the external terminals are respectively connected to an LSI device using wires so that a plurality of interconnections are formed between the LSI device and the external terminals, the lengths of the interconnections being equal.
It is yet another object of the present invention to provide an LSI package which can prevent any crosstalk between a pair of lines.
In order to achieve to above object, the LSI package further includes a double-layer structure having an upper layer and a lower layer provided with the plurality of lines thereon,
wherein the lines provided on the upper layer and the lines provided on the lower layer are offset by half a pitch, and
wherein, when a pair of lines having equal lengths for transmitting differential signals are provided on either one of the upper layer and the lower layer, a line on the other one of the upper layer and the lower layer positioned between the pair of lines is used as one of terminating resistance line and a power supply/ground line.
REFERENCES:
patent: 4489365 (1984-12-01), Daberkoe
patent: 5581126 (1996-12-01), Moench
patent: 5726860 (1998-03-01), Mozdzen
patent: 5844783 (1998-12-01), Kojima
patent: 5986893 (1999-11-01), Leigh et al.
patent: 5-114770 (1993-05-01), None
patent: 6-334104 (1994-02-01), None
Asada Kenji
Hamano Toshio
Ikemoto Yoshihiko
Armstrong, Westerman Hattori, McLeland & Naughton
Cunio Kamand
Fujitsu Limited
Gaffin Jeffrey
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