LSI Microprocessor having an error processing circuit

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G06F 300, G06F 1100

Patent

active

043171710

ABSTRACT:
An LSI microprocessor comprising an instruction fetch portion and an instruction execute portion which fetches an instruction and executes an instruction independently of each other under a microprogram control, a pipeline control being made while synchronizing the portions, the instruction fetch portion containing therein an error processing circuit, which receives an external memory error signal concerning a main memory and an internal protect error signal and which delivers a reset signal for clearing a microprogram counter and starting an error processing microprogram.

REFERENCES:
patent: 3573851 (1971-04-01), Watson et al.
patent: 3962682 (1976-06-01), Bennett
patent: 4003033 (1977-01-01), O'Keefe et al.
patent: 4050058 (1977-09-01), Garlic
patent: 4084236 (1978-04-01), Chelberg et al.
patent: 4087856 (1978-05-01), Attanasio

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