LSI logic synthesis device and method therefor

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364488, G06F 1750

Patent

active

055306543

ABSTRACT:
Logic synthesis device for LSI having a configuration divided into a plurality of hierarchical blocks specified by hierarchical design comprises a logic synthesis section which uses the logic description information describing the logic operation contents for each of the hierarchical blocks, information about location and area of the hierarchical blocks constituting the LSI and correspondence information between the logic operation contents described in the logic description information and the logic gate circuits physically described on LSI in order to make logic synthesis in and between hierarchical blocks and to adjust the delay times between the hierarchical blocks based on the block placement information.

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patent: 5331569 (1994-07-01), Iijima
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