LSI layout and method for fabrication of the same

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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29577C, 307207, 307213, 307215, 307241, 307242, 365104, H03K 1908, H03K 1920

Patent

active

040841057

ABSTRACT:
An LSI layout includes a logic function section and a series connection array of two MOSFETs, one end of which array is coupled to a power source voltage and the other end of which array is coupled to ground potential. A fixed logic output is produced at a junction point of the two MOSFETs by providing one MOSFET as an enhance-type MOSFET and providing the other MOSFET as a depletion type MOSFET. A logic circuit is provided which is connected with the junction point of the MOSFET array and with the logic section and is operable to couple the output of the logic section to an output side thereof. Two logic sections may be respectively associated with two logic circuits one of which is operable to couple the output of one logic section to an output thereof for its practical use and the other of which is operable not to couple the output of the other logic section to an output side thereof. The selection of the used section and the unused section is determined by the selection of either one of MOSFETs to depletion type. The LSI layout further may include a circuit section including MOSFETs. In that case, a single mask may be used in introducing a selected MOSFET of the MOSFET array and selected MOSFETs of the circuit section as depletion types. Such an LSI layout is suitable for the manufacture of many different kinds of LSI layouts with a minimized number of fabrication masks.

REFERENCES:
patent: 3678476 (1972-07-01), Ebertin
patent: 3731073 (1973-05-01), Moylan
patent: 3775693 (1973-11-01), Proebsting
patent: 3892596 (1975-07-01), Bjorklund
patent: 3914855 (1974-10-01), Cheney et al.
patent: 3981070 (1976-09-01), Buelow et al.
patent: 3983619 (1976-10-01), Kubo et al.
patent: 3988214 (1976-10-01), Tsunemitsu
patent: 3990045 (1976-11-01), Beausoleil et al.

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