LSI high-voltage timing circuit for MOS dynamic memory element

Details LSI high-voltage timing circuit for MOS dynamic memory element LSI high-voltage timing circuit for MOS dynamic memory element

1985-03-01

1987-06-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307482, 307578, 307443, 307264, 365104, 365203, H03K 458, H03K 17687, H03K 1710, G11C 1140

Patent

active

046773134

ABSTRACT:
A timing circuit with a high-voltage output has a one-stage structure and is designed to immediately start charging a booster capacitor with large capacitance so that its charging is completed within the precharge period and its charges are ready to be used in the subsequent active period. This reduces the delay time and the number of circuit elements. Thus, the circuits of this invention are adapted for large scale integration and may be combined to form a data output circuit.

REFERENCES:
patent: 4371795 (1983-02-01), Mulder et al.
patent: 4390797 (1983-06-01), Ishimoto
patent: 4395644 (1983-07-01), Misaizu
patent: 4521701 (1985-06-01), Reddy
patent: 4542307 (1985-09-01), Ikeda
patent: 4574203 (1986-03-01), Baba
patent: 4587446 (1986-05-01), Okumura
patent: 4587447 (1986-05-01), Baehring
Joynson et al., "Eliminating Threshold Losses in MOS Circuits by Bootstrapping Using Varactor Coupling, IEEE Journal of Solid State Circuits", vol. SC-7, No. 3, pp. 217-224, Jun. 1972.

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