LSI gate array having reduced switching noise

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307448, 307451, 307475, 307577, 307579, 307591, 307303, H03K 1716, H03K 19003

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active

047272660

ABSTRACT:
As the number of output circuit increases in LSI or VLSI circuit, there increases the chance of many large output circuits operates at a same instant, and it causes malfunction of logic by induced switching noise. In order to prevent such problem, the switching speed of driving buffer circuit for output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not affected so much, but the noise is decreased very much. The control of the switching capacity of the driving buffer circuit is performed by master slice technology. Such as perfectly opposite design concept to that of present LSI design has been proofed by experiments.

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patent: 4272830 (1981-06-01), Moench
patent: 4311925 (1982-01-01), Chang et al.
patent: 4394588 (1983-07-01), Gaudenzi
patent: 4430583 (1984-02-01), Shoji
patent: 4479067 (1984-10-01), Fujita
patent: 4504959 (1985-03-01), Heckenbach
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., Oct. 1980, pp. 5-14.
Patent Abstracts of Japan, vol. 7, No. 136, JP-A-58-51536, Jun. 14, 1983.
Patent Abstracts of Japan, vol. 6, No. 251, JP-A-57-148363, Dec. 10, 1982.
Proceedings of the 2nd International Conference on Semi-Custom ICs, "Introduction of an Ultra Fast 8000-Gate CMOS Gate Array", Nov. 23-25, 1982, pp. 1-7.

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