LSI fault insertion

Details LSI fault insertion LSI fault insertion

1986-02-04

1987-05-26

Smith, Jerry

Excavating

371 25, 371 27, G01R 3128, G06F 1100

Patent

active

046690816

ABSTRACT:
Apparatus and method for providing programmable fault insertion circuitry in a large scale integrated (LSI) circuit device thereby eliminating the need for external switches or relays to create faults. A fault parameter word is stored in a register and the outputs of the register are decoded to select the fault condition to be inserted by an interfacing circuit to the logic being tested. Test vectors and the fault parameter word are generated by a controller coupled to the integrated circuit and a test response from the integrated circuit is examined by the controller.

REFERENCES:
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patent: 4561095 (1985-12-01), Khan
R. L. Cormier, "Computer Fault Generator", IBM TDB vol. 11, No. 8. 1/1969, pp. 924-926.
A Logic Design Structure for LSI Testability, E. B. Eichelberger and T. W. Williams, 1977 Design Automation Conference, pp. 462-468.

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