LSI encoding device with pixel data blocking and vertical decima

Details LSI encoding device with pixel data blocking and vertical decima LSI encoding device with pixel data blocking and vertical decima

1993-01-04

1994-12-06

Powell, Mark R.

Television

Bandwidth reduction system

Data rate reduction

348403, 358433, H04N 1102

Patent

active

053715462

ABSTRACT:
An LSI device for encoding an image includes a dot sequential access unit for sequentially storing in an external storage image data arranged in a dot sequential manner, a block data output device for outputting block data from the storage, the block data including the pixel data of a predetermined number of lines and a predetermined number of columns, and a vertical decimating unit for conducting a vertical decimating operation for the block data. The LSI device employs only one memory to achieve the decimating operation and the blocking operation. As a result, the number of pins of the device and the size thereof can be decreased.

REFERENCES:
patent: 4764805 (1988-08-01), Rabbani et al.
patent: 4829378 (1989-05-01), LeGall
patent: 4916537 (1990-04-01), Nakayama et al.
patent: 5105271 (1992-04-01), Niihara
patent: 5136379 (1992-08-01), Ishii

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