LSI device with memory and logics mounted thereon

Details LSI device with memory and logics mounted thereon LSI device with memory and logics mounted thereon

1999-05-04

2001-03-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S063000, C365S189011

Reexamination Certificate

active

06205082

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-chip package on which a plurality of chips such as a memory device chip and a logic device chip are mounted, and, more particularly, to a novel structure which can implement fast transfer of data signals between both types of chips.
2. Description of the Related Art
A logic device, such as a microcontroller or a memory controller, and a memory device like a DRAM are connected together by a bus line, whereby a data signal like a stored data or an address is sent to the memory device from the logic device, and a data signal stored in the memory device is sent to the logic device.
FIG. 25
shows a conventional structure which has a logic device connected to a memory device. In
FIG. 25
, a logic device
10
and a memory device
20
are connected together by bus lines
5
, so that a data signal is transferred at a high speed in synchronism with a clock. Recently, the speed of transfer of data signals between the logic device
10
and the memory device
20
is getting faster and faster. Increasing the data transfer rate requires an increase in the number of bus lines or an increase in the clock frequency for data transfer. The former scheme increases the bus-lines occupying area on the board on which both devices are mounted, thereby increasing the dissipation power for driving the bus lines. The latter scheme is inadequate because it suffers a limitation to the transfer performance of the bus lines themselves as well as the device speed itself.
FIG. 26
shows the structure of a system LSI which has a logic section
2
and a memory section
3
embedded in a single chip. This structure can permit an improvement on the speed of data transfer between the logic section
2
and the memory section
3
. optimization of the logic section
2
and the memory section
3
however requires that both sections should be formed by separate processes, which together with the one-chip structure would increase the manufacturing cost.
Although designing a logic device and a memory device on a single chip is advantageous in improving the transfer speed, however since it increases the manufacturing cost, it is not practical. A promising method therefore is to construct a logic device and a memory device on separate chips and then to design those chips into a multi-chip structure.
But, any adequate means for accomplishing fast transfer of data signals between such two chips of the multi-chip structure has not been proposed so far. In particular, no structure which outputs a data signal from one chip in synchronism with a predetermined clock and allows the other chip to receive the data signal and transfer it inside has been proposed yet.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an inexpensive multi-chip device which has substantially the same data transfer rate as a one-chip device.
It is another object of this invention to provide a multi-chip device capable of implementing fast data transfer between chips in synchronism with a clock.
It is a further object of this invention to provide a memory device which can receive external data signals at a high speed.
To achieve the above objects, according to a first aspect of this invention, there is provided an LSI device on which a first chip and a second chip to be connected by lead lines are mounted, and in which
the first chip has an output circuit for outputting a data signal in response to an output clock, and a data output terminal connected to the output circuit,
the second chip has an input circuit for receiving the data signal, output from the output circuit, in response to a transfer clock generated from the output clock and sent to the second chip via the lead line for clock, and a data input terminal connected to the input circuit, and
the data output terminal in the first chip and the data input terminal in the second chip are arranged on opposing sides of both chips and are connected together via the lead line for data.
According to the first aspect of the invention, a data signal is output from the output circuit of the first chip and sent to the data input terminal in the second chip via the data lead line based on the output clock in first chip, which is sent to the second chip, and the input circuit in the second chip receives the data signal and transfers it inside in response to the transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.
To achieve the above objects, according to a second aspect of this invention, there is provided an LSI device on which a first chip and a second chip to be connected by lead lines are mounted, and in which
the first chip has an input circuit for inputting a data signal from the second chip in response to a transfer clock in the first chip, and a data input terminal connected to the input circuit,
the second chip has an output circuit for outputting a data signal in the second chip to the input circuit in response to an output clock generated from the transfer clock and sent inside the second chip via the lead line for clock, and a data output terminal connected to the output circuit, and
the data input terminal in the first chip and the data output terminal in the second chip are arranged on opposing sides of both chips and are connected together via the lead line for data.
According to the second aspect of the invention, a data signal is received at the data input terminal in the first chip and transferred inside based on the transfer clock in first chip, which is sent to the second chip, and a data signal is output from the output circuit in the second chip and sent to the data input terminal in the first chip via the data lead line in response to the output clock that has been generated from the transfer clock. In synchronism with a single reference clock in the first chip, therefore, fast transfer of a data signal to the first chip from the second chip can be implemented.
To achieve the aforementioned objects, according to a third aspect of this invention, each chip in the first and second aspects of the invention has a plurality of input circuits and a plurality of output circuits and their associated data input terminals and data output terminals are provided along their opposing sides. Also provided is a clock supply line which supplies the transfer clock or the output clock to the associated output circuits or input circuits at approximately the same timings.
This structure can ensure fast transfer of plurality of data signals between the first and second chips in synchronism with the reference clock in the first chip.


REFERENCES:
patent: 5642323 (1997-06-01), Kotani et al.
patent: 5710733 (1998-01-01), Chengson et al.
patent: 5838603 (1998-11-01), Mori et al.
patent: 5867448 (1999-02-01), Mann
patent: 5983331 (1999-11-01), Akamatsu et al.

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