Abrasive tool making process – material – or composition – With inorganic material – Metal or metal oxide
Reexamination Certificate
2001-07-02
2003-04-15
Marcheschi, Michael (Department: 1755)
Abrasive tool making process, material, or composition
With inorganic material
Metal or metal oxide
C051S307000, C051S308000, C106S003000, C438S692000, C438S693000
Reexamination Certificate
active
06547843
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a composition for polishing a metal layer and a barrier film during a production step of an LSI device, and more particularly, to such a polishing composition particularly suitable for polishing a multiple layer formed of a metal layer and a thin film, wherein the metal layer is formed of copper and the thin film is formed of a tantalum-containing alloy such as tantalum or tantalum nitride. The invention also relates to a method for producing an LSI device by use of the polishing composition.
BACKGROUND OF THE INVENTION
The degree of integration of LSI devices has increased year by year. One basic technique for realizing a high degree of integration is a polishing process. In a step for producing an LSI device, application of techniques for the polishing process such as buried metal polishing (i.e., the damascene method) for forming micro-wiring keeping pace with micro-scaling of a design rule is under way. However, enhancement of integration of an LSI device results in an increase in semiconductor surface roughness, generating steps that cause trouble such as breakage of wiring, an increase in resistance, or generation of electromigration. Such trouble causes problems such as a decrease in reliability. Solving the problems requires a planarization technique for compensating roughness between layers of the devices. CMP (chemical mechanical polishing) is one such technique.
Copper is an excellent wiring material, due to high electromigration resistance and low electrical resistance. Hitherto, there has been known no effective plasma etching method or method for wet-etching copper, which method can appropriately attain mechanical interconnection of copper parts. Thus, CMP of copper has been proposed as a practical technique for properly forming an interconnection part of copper parts provided on an LSI device. Accordingly, there is demand for an appropriate CMP composition for use in establishing interconnection of copper parts on an LSI device.
When copper is to be employed as wiring material, a certain barrier metal is formed in order to prevent diffusion of copper prior to the formation of copper film, since copper has a high diffusion coefficient in an interlayer insulation film. Examples of potential material for providing the barrier metal include Ta and TaN, which have excellent barrier properties. However, there arises a problem in that Ta and TaN are difficult to remove by polishing during performance of CMP. In general, when the ratio of the rate of polishing barrier metal to that of polishing copper is small, dishing, erosion, or a similar phenomenon occurs until the barrier metal is completely removed.
Upon performing CMP, copper and the barrier metal may be removed simultaneously through a single CMP step, or copper and the barrier metal may be removed respectively through two steps of CMP. In both cases, during a step for removing the barrier metal by polishing, the ratio of the rate of polishing a barrier metal formed of Ta or TaN to that of polishing copper is preferably controlled to 1.0 or more, so as to prevent occurrence of dishing or a similar phenomenon.
However, conventional polishing compositions cannot attain such a performance, and therefore, cannot be put into practice. For example, CMP slurry “EP-C4110” (product of Cabot Corp.), disclosed in proceedings of lectures of “Metal CMP
Tettei
-
Kensho,
” held by Denshi Journal (Feb. 27, 1998) (p. 84), exhibits a ratio of the rate of polishing Ta to that of polishing Cu of 1/12.
In this connection, the following two publications disclose conventional techniques related to the present invention, though they fail to disclose the polishing rate of barrier metal.
One of the publications is Japanese Patent Application Laid-Open (kokai) No. 10-46140 authored by the present inventors, disclosing a neutral LSI device polishing composition which comprises a carboxylic acid, an oxidizing agent, and water.
The other publication is Japanese Patent Application Laid-Open (kokai) No. 8-45934, disclosing an LSI device polishing composition containing abrasive grains which have been treated with an amino-group-containing surface treatment agent.
Japanese Patent Application Laid-Open (kokai) No. 10-46140 authored by the present inventors discloses a neutral LSI device polishing composition which comprises a carboxylic acid, an oxidizing agent, and water, but discloses neither use of abrasive grains which have been treated with a coupling agent nor polishing performance in relation to barrier metal. Furthermore, the kokai publication fails to disclose the teaching that the rate of polishing copper can be reduced by adjusting the pH of a polishing composition by use of at least one alkaline substance selected from among alkali metal hydroxides such as NaOH and KOH; alkali metal carbonates such as Na
2
CO
3
and K
2
CO
3
; alkali metal hydroxides such as Mg(OH)
2
and Ca(OH)
2
; and hindered amines such as 2,2,6,6-tetramethyl-4-hydroxypiperidine, 2,2,6,6-tetramethylpiperidine, 2,2,6,6-tetramethyl-4-piperidone, 2,2,4,4,6-pentamethyl-2,3,4,5-tetrahydropyrimidine, 1,9-diaza-2,2,8,8,10,10-hexamethyl-spiro[5.5]undecan-4-one, and 6-aza-7,7-dimethylspiro[4.5]decan-9-one. Thus, the present invention cannot be easily attained solely on the basis of that kokai publication, and therefore the patentability of the present invention is not impaired.
The aforementioned Japanese Patent Application Laid-Open (kokai) No. 8-45934 discloses that a surface of the metal wiring layer formed on the semiconductor substrate is polished by use of abrasive grains which have been treated with an amino-group-containing surface treatment agent.
This technique, clearly described in ibid. (p. 2, right column, line 16-42), is employed for preventing, through enhancement of dispersibility of silicon oxide micrograms in an acidic solution, generation of damage; i.e., scratches, in surfaces of a multi-layer wiring layer and an interlayer insulating film of an LSI device. To attain this object, there have been proposed silicon oxide micrograms on which surfaces are covered with a basic layer formed through surface treatment by use of an amino-group-containing organosilicon compound. A working example of the above patent publication describes a process of polishing a tungsten wiring layer by use of silicon oxide micrograms which have been surface-treated by reaction in solution with &ggr;-aminopropyltriethoxysilane or N-2-aminoethyl-3-aminopropyltrimethoxysilane.
This technique does not impair the patentability of the present patent application, for the reasons described hereinbelow.
(1) The technique described in that patent specification is intended to enhance dispersibility of silicon oxide micrograms in an acidic solution. For example, as described in Example 1, K
2
[Fe(CN)
6
]+KH
2
PO
4
are added to a slurry, to thereby adjust the pH to 5.0, which corresponds to an acidic pH region.
In contrast, the composition of the present invention has a pH of 5.5-10.0, which corresponds to a neutral to weakly alkaline pH region. Therefore, the above effect for enhancing dispersibility of silicon oxide micrograms through surface treatment cannot be attained.
Furthermore, the composition of the present invention can control the ratio of the rate of polishing barrier metal to that of polishing copper and can reduce the rate of dissolving copper, because the pH of the composition is adjusted within a neutral to weakly alkaline pH region. Therefore, the composition of the present invention is not taught by the above patent publication which premises use of the composition in an acidic pH region.
(2) The above patent publication provides no description in relation to the rate of polishing wiring layer metal or barrier metal. Although a process of polishing a tungsten wiring layer is described in an Example, the process is evaluated in terms of only the scratch status.
In the present invention, one of the problems to be solved is controlling within a predetermined range the ratio of the ra
Kido Takanori
Shimazu Yoshitomo
Uotani Nobuo
Marcheschi Michael
Showa Denko K.K.
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