LSI Circuitry conforming to level sensitive scan design (LSSD) r

Details LSI Circuitry conforming to level sensitive scan design (LSSD) r LSI Circuitry conforming to level sensitive scan design (LSSD) r

1979-07-26

1981-11-03

Atkinson, Charles E.

Excavating

324 73R, 364900, 371 21, G01R 3128, G06F 1100

Patent

active

042989809

ABSTRACT:
An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La] Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

REFERENCES:
patent: 3582633 (1971-06-01), Webb
patent: 3675200 (1972-07-01), Bossen et al.
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 3815025 (1974-06-01), Jordan
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4006492 (1977-02-01), Eichelberger et al.
patent: 4051352 (1977-09-01), Eichelberger et al.
patent: 4051353 (1977-09-01), Lee
patent: 4063078 (1977-12-01), Das Gupta et al.
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
patent: 4100605 (1978-07-01), Holman
patent: 4167041 (1979-09-01), Curlander et al.
patent: 4225957 (1980-09-01), Doty, Jr. et al.
Balasubramanian, P. S. et al., "Testing LSI Memory Arrays Using on Chip I/O Shift Register Latches" in IBM Tech. Disc. Bull., vol. 17, No. 7, Dec. 1974, pp. 2019-2020.
Ross, B. M. et al., "Combined Test Scanning and Serial-Deserializing Shift _Register" in IBM Tech. Discl. Bull., vol. 19, No. 2, Jul. 1976, pp. 480-481.
Dimitri, K. E., "Delay Testing and Diagnosis of LSSD Shift Register Strings" in IBM Tech. Discl. Bull., vol. 20, No. 1, Jun. 1977, pp. 307-312.
Hsu, F. et al., "Selective Control of Off-Subassembly Drivers To Test Logic Systems" in IBM Tech. Discl. Bull., vol. 20, No. 11B, Apr. 1978, pp. 4728-4730.
Williams, Single Clock Shift Register Latch, IBM Technical _Disclosure Bulletin, vol. 16, No. 6, Nov. 1973.
Berglund, Level-Sensitive Scan Design Tests, Chips, Boards, _Systems, Electronics, Mar. 15, 1979, pp. 108-110.
Correia et al., 14 Design Automation Conference Proceedings, Introduction to AN LSI Test System, Jun. 20-22, 1977, pp. 460-461.
Eichelberger et al., A Logic Design Structure for LSI Testability, 14th Design Automation Conference Proceedings, Jun. 20-22, pp. 462-468, 1977.
Godoy et al., Automatic Checking of Logic Design Structures for Compliance with Testability Ground Rules, 14th Design Conf. pp. 469-478.
Botoroff et al., Test Generation for Large Logic Networks, 14th Design Automation Conference Proceedings, Jun. 20-22, 1977, pp. 479-485.
Hsieh et al., Delay Test Generation, 14th Design Automation Conference Proceedings, Delay Test Generation, pp. 486-491.
Storey et al., Delay Test Simulation, 14th Design Automation Conference Proceedings, Jun. 20-22, 1977, pp. 492-494.

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