Excavating
Patent
1984-09-21
1987-06-02
Atkinson, Charles E.
Excavating
324 73R, 371 27, G01R 3128
Patent
active
046708774
ABSTRACT:
According to this invention, an LSI circuit is provided with a pseudorandom data generating circuit for producing pseudorandom data and a timing signal generating circuit for producing test timing signals in synchronism with a control input timing signal necessary for the operation of an internal logic circuit. The LSI circuit has two input lines, a control input line and a data input line. The LSI circuit further includes a circuit, which selectively supplies the timing signals from the timing signal generating circuit on the control input line and selectively supplies the pseudorandom data from the psuedorandom data generating circuit on the data input line. Consequently, the LSI circuit automatically generates control input signals and data input signals within itself to carry out the self-checking operation.
REFERENCES:
patent: 3924181 (1975-12-01), Alderson
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komonytsky
patent: 4551838 (1985-11-01), Gannett
Konemann et al., Built-in Test for Complex Digital Integrated Circuits, IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980, pp. 315-319.
Le Blanc, LOCST: A Built-in Self-Test Technique, IEEE Design & Test, Nov. 1954, pp. 45-52.
Atkinson Charles E.
Kabushiki Kaisha Toshiba
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