LRU pointer updating in a controller for two-way set associative

Details LRU pointer updating in a controller for two-way set associative LRU pointer updating in a controller for two-way set associative

1996-06-27

1998-03-03

Gossage, Glenn

395463, 395487, G06F 1212

Patent

active

057245479

ABSTRACT:
A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. There are two lines selected during a line fill to one of the ways. A least recently used (LRU) pointer selects which way to fill on a line fill cycle. The right way is selected for a line fill in response to right hit signal provided that the LRU pointer points to the right way. The LRU pointer is flipped to point to the left way upon the filling of the right line of the right way. The left way is selected for a line fill in response to a left hit signal provided that the LRU pointer points to the left way. The LRU pointer is flipped to point to the right way upon the filling of the left line of the left way.

REFERENCES:
patent: 4363095 (1982-12-01), Woods et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5339399 (1994-08-01), Lee et al.
patent: 5530833 (1996-06-01), Iyengar et al.

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