Lower address line prediction and substitution

Details Lower address line prediction and substitution Lower address line prediction and substitution

1995-05-19

1998-05-19

Teska, Kevin J.

Boots, shoes, and leggings

395853, 395855, 395281, 395309, 364DIG1, G06F 930, G06F 104

Patent

active

057548250

ABSTRACT:
An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter. The output of the second counter is merged into the low order address signal of the bus interface devices to properly index the second word of the burst transfer cycle.

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Eisa with Enhanced Master Burst (EMB) Addendum, Rev. 1.0, BCRP Services, Inc., .COPYRGT.1993 BCRP Services, INC.
Product Preview: 1-Line To 6-Line Clock Driver with Selectable Polarity, .COPYRGT.1994 Texas Instruments.

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