Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-02-03
2002-08-13
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S112000, C326S083000, C330S253000
Reexamination Certificate
active
06433605
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit clock circuitry and more particularly to such clock circuitry including a receiver having an input impedance causing a wire carrying a clock wave to the receiver to present to a driver an impedance having a resistance-capacitance (RC) time constant that is a relatively small fraction of a cycle of the clock wave.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) chip frequently includes clock trees to distribute clock waves to physically separated destination (i.e., receiver) circuits. Typically, an off-chip, external clock source provides clock waves to a plurality of clock tree branches or segments resident on the IC chip. Each branch or segment of the clock tree carries clock waves to a respective one of the physically separated destination circuits.
Ideally, the clock waves delivered by any given branch arrive at the associated destination circuit in synchronism or in phase with the other clock waves arriving at their respective destination circuits. In this way, synchronism is maintained across the entire integrated circuit chip. In such an ideal case, the respective clock waves are said to exhibit zero clock skew at the various destination circuits. The term “clock skew” represents the relative time delay between corresponding clock waves as they exit their respective branches. For example, the clock skew between two branches of the clock tree is the time delay between the rising edges of corresponding clock waves exiting the two branches.
Although the ideal clock tree delivers clocks with zero skew, in reality, there are many factors that adversely affect, i.e., increase, clock skew in an IC chip, to prevent zero clock skew from being obtained throughout the chip. One factor is material processing variations inherent to the IC chip fabrication process; chip components can only be fabricated to predetermined tolerances so that different nominally identical components at different locations on the chip have different characteristics. Other factors include power supply and temperature variations across the chip. Since large IC chips are susceptible to both spatial and temporal variations in localized temperature and power supply voltage while operating, and since chip component characteristics and behavior are influenced by such variations, clock skew correspondingly varies both spatially and temporally across the chip. As the size of an IC chip increases, the variability of these factors and thus the variability of clock skew, worsens.
Large IC chips require clock lines of relatively long length to carry clock waves throughout the chip. In large chip applications, these relatively long clock lines and the delays they introduce, as well as the other factors affecting clock skew described previously, combine to exacerbate clock skew. In addition, the requirement to operate IC chips at high frequency (e.g., at 500 MHz or more), further requires tight control and clock skew minimization. Thus, an important challenge presented by increasing IC chip size and clock operating frequency is that of controlling clock skew to within acceptable tolerances.
FIG. 1
is a circuit diagram of a conventional clock tree distribution segment for distributing clock waves on an IC chip carrying the segment. The circuit of
FIG. 1
is on an IC chip and includes spaced clock wave driver
4
and clock wave receiver
6
as well as wire or clock line
2
that is connected between the driver and receiver. Driver
4
usually responds to clock waves in the form of a sequence of clock pulses derived from a clock source (not shown) that is not on the IC chip. Driver
4
derives at output terminal
10
a sequence of amplified clock waves in the form of clock pulses. Terminal
10
, at the junction of the drains of complementary field effect transistors
11
and
13
having gates driven in parallel by the clock pulses from clock input
12
, is connected to a first end of single ended line
2
to supply the derived clock pulses to the first end of the clock line. The clock waves traverse clock line
2
and exit at a second end thereof to be injected into input terminal
14
of clock wave receiver
6
.
Receiver
6
includes complementary FETs
17
and
19
having gates driven in parallel by the pulses at terminal
14
of line
2
and drains connected to a common terminal
16
, where the output is derived. The FETs of driver
4
and receiver
6
are connected across power supply rails connected to DC power supply terminals +Vdd and ground so the sources of N-channel FETs
11
and
17
are grounded and the sources of P-channel FETs
13
and
19
are at +Vdd; in the typical prior art circuit, Vdd=3 Volts. The clock pulses propagating along line
2
are attenuated because of the substantial impedance of the line, are phased delayed because of the substantial resistance-capacitance (RC) time constant of the line, and are subject to noise on the line which is coupled to terminal
14
. Receiver
6
responds to the degraded clock pulses at terminal
14
to amplify the pulses almost to the rail-to-rail voltages +Vdd and ground.
When a plurality of conventional clock tree distribution segments of the type illustrated in
FIG. 1
distribute clocks across an IC chip, clock skew problems arise between the various clock distribution segments. One reason these conventional circuits contribute to clock skew is because they inherently impart large time delays to the clock waves. Since these circuits themselves introduce in part large time delays to the clock waves, even small changes or variations in this large delay, as between the various clock tree segments, contribute significantly to an increase in clock skew. These changes in the delay between the various clock segments arise as a result of small variations in operating characteristics and behavior of the individual components comprising the individual clock segments.
The following example serves to illustrate this point. Referring again to the conventional clock circuit of
FIG. 1
, assume that clock line
2
and input terminal
14
of receiver
6
together present an input impedance to output
10
of driver
4
on the order of several hundred ohms, due primarily to the high gate-source impedance FET receiver
6
presents to terminal
14
and the driver
4
output impedance, as well as the impedance of line
2
. Typically, clock line
2
presents a capacitive load of approximately 2 pico farads (pF) to output terminal
10
of driver
4
. With these exemplary assumptions, a typical RC time constant of approximately several hundred picoseconds is presented to the clock pulses at output terminal
10
of driver
4
. In an integrated circuit chip operating at a frequency of, for example, 1 GHz, which translates to clock periods or cycles on the order of 1 nanosecond (ns), the several hundred ps time delay introduced by the conventional clock circuit of
FIG. 1
represents a considerable portion of each half cycle pulse of each clock period. Thus, small changes in delay times between clock segments, due to the factors discussed previously, can cause clock skew of a considerable portion of one clock cycle. Clearly, for IC chips operating at high frequencies wherein clock synchronization across the chip is required, such clock skew is disadvantageous and the conventional clock circuit of
FIG. 1
has substantial problems in controlling clock skew to within acceptable tolerances.
Although the foregoing approximation serves as a useful example to illustrate the adverse effect of the large interconnect delay of the circuit of
FIG. 1
on clock skew, characterizing the RC delay on the interconnect mathematically is useful for comparative purposes. The following generalized equation, Equation (1), characterizes the total RC delay time (Delay) of clock line
2
between driver
4
and receiver
6
Delay
=
R
int
C
int
2
(
Rdr
+
R
int
/
3
+
Rcvr
Rdr
+
Rrcv
+
R
int
)
+
Rdr
&
Cunningham Terry D.
Tra Quan
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