Coded data generation or conversion – Digital code to digital code converters
Reexamination Certificate
2001-01-16
2004-09-07
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
C341S058000
Reexamination Certificate
active
06788222
ABSTRACT:
TECHNICAL FIELD
The present invention relates to high-speed bus technologies, and more particularly, relates to low weight data encoding circuitry and methods of encoding data sent out on a data (I/O) bus such that there is minimal net current drawn from the local power delivery system due to switching I/O cells across a predetermined number of bits.
BACKGROUND
In recent years, technological advances in electronic systems have demanded ever-higher functionality, ever-faster circuit speeds, and always increasing interconnection density. Semiconductor technology has well kept up with advancing system requirements. However, the basic interconnection technology, namely printed circuit boards and substrates for high-speed digital components and active circuits, such as processors, chipsets, and I/O devices, has not always followed due to the complex nature of impedance, switching noise, system noise, power distribution inductances and decoupling characteristics.
For example, I/O cells of a high-speed active circuit, such as a chipset or a processor, require a power-ground decoupling network that will deliver high frequency transient current to the switching output transistors (i.e., logic gates). If the network is not designed properly, the system performance will be degraded.
Currently, there are two methods that may be used to ensure that the high frequency transient current is cleanly delivered to the switching output transistors of the active circuit.
One method is known as the traditional “heavy decoupling” method which relies on large numbers of capacitors placed in very close proximity to the I/O cells either on the chip package or the printed circuit board (PCB) to provide a charge reservoir and deliver high frequency current to the I/O cells. However, if there is a significant amount of inductance in series with the decoupling capacitance (i.e., planes, vias, bond wires, etc.), the transient current that can be instantaneously delivered to the I/O cells will be limited, and switching noise will be injected onto the power delivery system which can significantly degrade both the timing and the signal integrity if too many I/O cells are switching simultaneously. The extra inductance is typically caused by the plane inductance of the chip package/PCB (i.e., physical distance to the capacitor), and via structures used to connect the capacitors to the appropriate power planes. These signal integrity and timing distortions often precipitate severe distortions in modern chip designs. For instance, validation vehicles for advanced processors such as Pentium® IV manufactured by Intel Corp., show severe waveform distortions on the front side bus (FSB) due to resonance phenomena that are directly caused by insufficient capacitance at the chipset. In addition, simulations performed during the design of Pentium® IV systems indicate a 125 ps timing skew impact due to inadequate decoupling at the chipset. One way to minimize signal and timing distortion is to dramatically increase the amount of capacitance per I/O cell on the die and minimize the inductance. However, the production cost for chipsets will be excessive.
The second method is known as the “data bus inversion” method which seeks to invert ½ of the system bus (the left half or the right half) if the majority of the data bits from the I/O cells are switching high. This will decrease the amount of transient current flowing into the local decoupling network and reduce the total switching noise caused by inductances inherent in the local power delivery system. However, large inductive current loops are created because the current balance is not distributed across the system bus, and the total current drawn through the local decoupling network is not minimized sufficiently for modem high speed designs.
As a result, there is no way to sufficiently decouple active circuits such as chipsets or processors so as to adequately meet the power delivery demands of the I/O cells with minimal cost and real estate (physical space). It is also very expensive to add large amounts of on-die capacitance and there is physically no room on the chipset to implement solutions usually used on typical processors, such as land side or die side capacitors, which are the only options known that will increase the capacitance without dramatically increasing the series inductance. Moreover, as speeds increase, the amount of tolerable inductance will become so small that discrete capacitors are entirely infeasible for I/O decoupling purposes.
Accordingly, there is a need to circumvent problems inherent with the “heavy decoupling” and “data-bus inversion” techniques so as to ensure signal integrity and minimize timing distortion. Also needed is a solution to encode data sent out on an I/O bus such that the net current drawn from the local power delivery system is minimized, and the switching noise is significantly reduced, if not entirely eliminated.
REFERENCES:
patent: 5940018 (1999-08-01), Kim et al.
patent: 6304196 (2001-10-01), Copeland et al.
patent: 6366223 (2002-04-01), Lee et al.
Hall Stephen H.
Leddige Michael W.
Intel Corporation
Kenyon & Kenyon
Nguyen John B
Young Brian
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