Low-voltage triple-well non-volatile semiconductor memory

Details Low-voltage triple-well non-volatile semiconductor memory Low-voltage triple-well non-volatile semiconductor memory

1998-04-13

1999-12-07

Hoang, Huan

Static information storage and retrieval

Floating gate

36518505, G11C 1604

Patent

active

059994436

ABSTRACT:
A new structure of a triple-well non-volatile semiconductor memory cell array and a method of fabricating the memory arrays are described. The circuit layout of the memory array not only includes the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of contact windows, further increasing the packing density of the memory array. The key point of the method is the triple-well formation inside the silicon substrate that lowers the operational voltage of periphery circuit. Furthermore, there are two additional isolation regions between two adjacent metal lines, which can minimize the possibility of cross talk due to shirking spacing.

REFERENCES:
patent: 5029139 (1991-07-01), Paterson
patent: 5691938 (1997-11-01), Yiu et al.

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