Low-voltage triggering electrostatic discharge protection

Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive

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361 56, 257355, H02H 322

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active

059826002

ABSTRACT:
Systems and methods are described for providing low-voltage triggering electrostatic discharge (ESD) protection in the context of integrated circuits. A low-voltage triggering electrostatic discharge protection circuit has a low trigger voltage and can turn on quickly to provide a low resistance path. The protection circuit can be employed in power bus, input, and input/output pin ESD protection configurations. This protection circuit is compatible with complementary metal oxide semiconductor (CMOS) processes. High ESD performance can even be achieved with devices fabricated in accordance with advanced CMOS processes.

REFERENCES:
patent: 4937639 (1990-06-01), Yao et al.
patent: 5239440 (1993-08-01), Merrill
patent: 5246872 (1993-09-01), Mortensen
patent: 5262344 (1993-11-01), Mistry
patent: 5270565 (1993-12-01), Lee et al.
patent: 5276350 (1994-01-01), Merrill et al.
patent: 5301084 (1994-04-01), Miller
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5635746 (1997-06-01), Kimura et al.
patent: 5701024 (1997-12-01), Watt
patent: 5710452 (1998-01-01), Narita
patent: 5717559 (1998-02-01), Narita
Amerasekera, A. et al., "The Impact of Technology Scaling on ESD Robustness and Protection Circuit Design", EOS/ESDosium Proceedings, Las Vegas, NV, Sep. 1994, pp. 6.1.1-6.1.9.
Chatterjee, A. et al., "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, vol. 12, No. 1, Jan. 1991, pp. 21-22.
Duvvury, C. et al., "Internal Chip ESD Phenomena Beyond the Protection Circuit", IEEE Transactions on Electron Devices, vol. 35, No. 12, Dec. 1988, pp. 2133-2139.
Johnson, C. et al., "Two Unusual HBM ESD Failure Mechanisms on a Mature CMOS Process", EOS/ESD Symposium Proceedings, Lake Buena Vista, FL, Sep. 1993, pp. 5B.4.1-5B.4.7.
Duvvury, C. et al., "ESD Protection Reliability in 1.mu.M CMOS Technologies", IEEE 24th Annual Proceedings, Reliability Physics 1986, Anaheim, CA, Apr. 1986, pp. 199-205.
Duvvury, C. et al., "Achieving Uniform nMOS Device Power Distribution for Sub-micron ESD Reliability", IEEE, New York, 1992, pp. 6.1.1-6.1.4. (No Month).
Duvvury, C. et al., "Dynamic Gate Coupling of NMOS For Efficient Output ESD Protection", IEEE 30th Annual Proceedings, Reliability Physics 1992, San Diego, CA Mar. 1992, pp. 141-150.
Polgreen, T. et al., "Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow", IEEE Transactions on Electron Devices, vol. 39, No. 2, Feb. 1992, pp. 379-388.

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