Automatic temperature and humidity regulation – Motors – Electric
Reexamination Certificate
2001-05-08
2003-09-23
Tanner, Harry B. (Department: 2858)
Automatic temperature and humidity regulation
Motors
Electric
C236S09100C
Reexamination Certificate
active
06622927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrical circuits, and in particular to a thermostat circuit with an output that indicates when the circuit's temperature is above or below a certain predetermined value.
2. Description of the Related Art
FIG.
1
—Prior Art
FIG. 1
shows a block diagram of a prior art thermostat circuit
100
. Thermostat circuit
100
comprises a constant voltage generator
105
, a proportional to absolute temperature (“PTAT”) voltage generator
110
, and a current comparator
115
. The constant voltage generator
105
generates a reference voltage V
REF
which is fed into the comparator
115
. Similarly, the PTAT voltage generator
110
generates a PTAT voltage V
PTAT
which is fed into the comparator
115
. When V
PTAT
>V
REF
, the output
120
is one logic state. When V
REF
>V
PTAT
, the output
120
is a different logic state.
Because V
PTAT
is proportional to temperature, this prior art thermostat circuit indicates when the circuit's temperature is above or below a certain temperature. V
REF
is set to equal V
PTAT
at this temperature.
There are at least two disadvantages associated with the circuit of FIG.
1
: (i) it will not function properly for very low supply voltages, and (ii) it requires a separate constant value as a reference. In addition, it is always desirable to have a thermostat circuit with better temperature sensitivity.
FIG.
2
—Prior Art
FIG. 2
shows a prior art PTAT current generator. This circuit is built with current sources I
1
-I
2
, npn bipolar junction transistors Q
1
-Q
2
, resistor R
1
, and operational amplifier (“opamp”) A
1
. Opamp A
1
has a noninverting input terminal (node n
1
), an inverting input terminal (node n
2
), and an output terminal (node n
3
).
Current sources I
1
-I
2
are implemented so that each current source produces a substantially equal current I
PTAT
. This can be done, for example, by utilizing PMOS transistors. In such an implementation, the sources of the PMOS transistors are connected to V
cc
, and the gates of the PMOS transistors are connected together in a current mirror configuration to node n
3
.
Transistor Q
2
is N times larger in size than transistor Q
1
. Initially, with Q
2
larger than Q
1
, and equal current from I
1
-I
2
, the voltage across Q
1
will be N times larger than the voltage across Q
2
. Thus, node n
2
will be driven higher than node n
1
. This will cause the voltage at node n
3
to decrease. Decreasing the voltage at node n
3
causes current I
PTAT
from current sources I
1
-I
2
to increase. Current I
PTAT
will increase until the voltage across resistor R
1
balances the voltage difference between transistors Q
1
and Q
2
.
The voltage difference between transistors Q
1
and Q
2
is proportional to absolute temperature, and can be expressed as:
Δ
V
BE
=
kT
q
·
ln
(
N
)
(
1
)
The current I
PTAT
is determined by a PTAT voltage drop on the resistor R
1
:
I
PTAT
=
Δ
V
BE
R
1
·
kT
q
·
R
1
·
ln
(
N
)
(
2
)
FIG.
3
—Prior Art
FIG. 3
shows a prior art V
BE
current generator. This circuit is built with current sources I
3
-I
4
, npn bipolar junction transistor Q
3
, resistor R
2
, and opamp A
2
. Opamp A
2
has a noninverting input terminal (node n
11
), an inverting input terminal (node n
12
), and an output terminal (node n
13
).
Current sources I
3
-I
4
are implemented so that each current source produces a substantially equal current I
VBE
. This can be done, for example, by utilizing PMOS transistors, as described above with respect to current sources I
1
-I
2
.
Because current sources I
3
-I
4
produce a substantially equal current I
VBE
, the voltage across transistor Q
3
appears across resistor R
2
. Therefore, the current I
VBE
is given by:
I
VBE
=
V
BE
1
R
2
(
3
)
SUMMARY OF THE INVENTION
In accordance with the present invention, a thermostat circuit is provided which (i) works properly with very low supply voltages, (ii) does not need a separate constant value as a reference, and (iii) has improved temperature sensitivity.
In accordance with the present invention, as illustrated in
FIG. 4
, current I
PTAT
from the prior art PTAT current generator and current I
VBE
from the prior art V
BE
current generator are fed into a current comparator. When I
VBE
>I
PTAT
, the output is one logic state (either high or low). When I
PTAT
>I
VBE
, the output is a different logic state (either low or high).
Another aspect of the present invention is the implementation of the I
PTAT
and I
VBE
current generators. One implementation shown in
FIGS. 5 and 8
uses only substrate pnp bipolar devices, which are the bipolar devices usually available in CMOS technology. Using only substrate pnp bipolar devices has the additional advantage of an operating supply voltage that could be below 1 V.
Another implementation is shown in
FIGS. 6 and 9
which has improved power supply rejection. Improved power supply rejection is obtained by cascoding current source transistors M
1
and M
2
using cascode transistors M
5
and M
6
. And yet another implementation shown in
FIGS. 7 and 8
includes a secondary loop for biasing cascode transistors M
1
and M
2
properly when the voltage between nodes n
11
and n
12
is not I
VBE
.
Another aspect in accordance with the present invention is the implementation of a current comparator. In one embodiment shown in
FIG. 11
, the current comparator is implemented so as to enable a hysteresis behavior.
Another aspect in accordance with the present invention is a circuit shown in
FIG. 12
which can be used in order to test or tune a low-voltage thermostat circuit in accordance with the present invention at room temperature.
REFERENCES:
patent: 2949237 (1960-08-01), De Wilde
patent: 5070932 (1991-12-01), Vlasak
patent: 5231848 (1993-08-01), Farr
patent: 5463874 (1995-11-01), Farr
Friedman Jay
Opris Ion E.
Fliesler Dubb Meyer & Lovejoy LLP
Tanner Harry B.
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