Low voltage swing circuits for low power clock distribution and

Details Low voltage swing circuits for low power clock distribution and Low voltage swing circuits for low power clock distribution and

1996-11-07

1998-12-15

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327589, 327165, G06F 104

Patent

active

058501576

ABSTRACT:
A clock distribution system for low power operation. Such a clock distribution system includes a global clock generation circuit coupled to generate a global clock signal. This global clock signal is received by a local clock generation circuit which generates a local clock signal. While the system has an operating voltage generally used throughout the system, at least one of the global clock signal and the local clock signal is a small swing clock signal which has a voltage swing substantially less than the operating voltage of the system.

REFERENCES:
patent: 5469116 (1995-11-01), Slemmer
Bazes, Mel, "Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers", IEEE Journal of Solid-State Circuits, vol. 26, No. 2, Feb. 1991, pp. 165-168.
Kojima, Hirotsugu, Satoshi Tanaka and Katsuro Sasaki, "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry", 1994 Symposium on VLSI Circuits Digest of Technical Papers, 1994 IEEE, pp. 23-24.
De Man, Erik, and Matthias Schobinger, "Power Dissipation in the Clock System of Highly Pipelined ULSI CMOS Circuits", IWLPD 1994 Workshop Proceedings, pp. 133-138.

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