Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-02-02
2001-03-13
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185280, C365S185060
Reexamination Certificate
active
06201732
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention pertains to electronic memories and in particular to nonvolatile memory cells and cell organization suitable for operation with byte alterability of the nonvolatile information stored in the memory.
2. Prior Art
There is a long history of nonvolatile memory devices and more particularly electrically erasable programmable read only memory (EEPROM) devices. All prior art commercial byte alterable EEPROMs have used N channel devices as the memory transistor. Such an N channel EEPROM cell
10
typical of current technology is shown in the top view of
FIG. 1
a
and the cross section of
FIG. 1
b.
As shown in
FIG. 1
a
there are two layers of polycrystalline silicon
13
and
14
formed on and insulated from silicon substrate
24
. The cell includes select transistor
29
and memory transistor
28
. The substrate under memory transistor
28
is doped P type except where locally doped N type to form source/drain regions
16
and
23
. The first layer of polycrystalline deposited is called poly
1
. The poly
1
feature
14
has no connections to other conductors and is therefore referred to as a floating gate. This portion of the poly
1
layer forms the gate of memory transistor
28
. The second layer of polycrystalline silicon, called poly
2
, is used to form a transistor
29
, having polycrystalline silicon gate
12
, that acts as a select transistor between contact
19
and memory transistor
28
. Poly
2
layer is also used to form control gate
13
of memory transistor
28
, which is capacitively coupled to floating gate
14
.
N type region
15
is located under a thin tunnel oxide window
11
. Region
15
is used during programming and erasing. (In this application, the IEEE standard
1005
will be followed consistently for nomenclature. Therefore, programming is defined as putting electrons onto the floating gate and erasing is defined as removing electrons from the floating gate.) There is also a buried diffusion
17
on the source side of the memory transistor
28
. This is included merely so that the channel length is not alignment sensitive and could be omitted without loss of functionality. The buried diffusions are so called because they lie under the polycrystalline silicon layers. (In some designs they also lie under the field oxide.) Thick field oxide
18
, which exists outside of the “T” shaped region of thin oxide bounded by the heavy lines in
FIG. 1
a
, provides isolation between the transistors and the N type diffusions where desired. The regions under field oxide
15
may have enhanced P type doping relative to the regions under the gates in order to raise the threshold voltages of the parasitic field transistors.
Typical operation will have floating gate
14
charged positively with respect to ground when erased and charged negatively with respect to ground when programmed. To read memory transistor
28
, control gate
13
is grounded and gate
12
of select transistor
29
is biased positively to provide a low resistance path from its drain contact
19
to drain
15
of memory transistor
28
. Drain contact
19
provides connection to metal bit line
25
as is seen in the cross section view of
FIG. 1
b
(the metal is omitted from the top view of
FIG. 1
a
in the interests of clarity). Bit line
25
is biased at a modest positive voltage (e.g. 2 V) and the common source line
16
is biased at ground. If floating gate
14
is erased, current can flow from bit line
25
to source region
16
. If floating gate
14
is programmed, memory transistor
28
is in a nonconducting state and no current flows. The presence or absence of current flow is sensed to determine the state stored by memory transistor
14
.
The oxide in tunnel window
11
is typically about 10 nm thick. To program memory cell
28
, floating gate
14
must be capacitively coupled to a sufficiently positive potential with respect to drain
15
that a field of about 10 MV/cm appears across tunnel oxide
11
. This is accomplished by biasing poly
2
control gate
13
at about 20 V while biasing select gate
12
at a sufficiently high potential that select transistor
29
is conducting with bit line
25
at ground potential. Under these conditions, drain region
15
provides a source of electrons on the cathode side of tunnel oxide
11
. With 10 MV/cm appearing across tunnel oxide
11
, Fowler-Nordheim tunneling occurs and charges floating gate
14
negatively.
To erase memory transistor
28
, the bias across tunnel oxide
11
must be reversed. This is accomplished by applying a high bias to drain
15
of memory transistor
28
while poly
2
control gate
13
is biased at ground in order to keep control gate
13
capacitively coupled to a low voltage. The high voltage is applied to drain
15
of memory transistor
28
by applying the desired voltage to bit line
25
while gate
12
of select transistor
29
is biased at a potential that is higher than the desired voltage by at least the threshold voltage of select transistor
29
.
The operation of this cell in an array can be understood with reference to
FIGS. 2
a
and
2
b
, which shows a portion of a prior art memory array
38
including a single word line
31
and associated bit lines
32
-
0
through
32
-
7
, thereby forming a portion of a memory capable of storing a single 8 bit word. (In this and subsequent schematic drawings, the transistor gate with a small notch directed at the channel region is used indicate a transistor in which one portion of the gate oxide has been thinned to enhance the tunneling current.) To write a desired data pattern into a word, all bits of the word are first programmed and then selected bits are erased to achieve the desired pattern. Selection of the word to be programmed is achieved with the combination of word line
31
and word line select transistor
37
in
FIG. 2
b
. A high voltage, V
PP
+V
TN
, where V
PP
is a positive programming voltage (typically approximately 18 volts) and V
TN
is the threshold voltage of an N channel transistor (typically approximately 4 volts with 18 V of source bias), is applied to word line
31
to select the desired row of the memory array. V
PP
is applied to column
35
associated with the desired word. This voltage passes through word select transistor
37
to the control gates
34
-
0
through
34
-
7
of all of the transistors in the word to be programmed. During this program operation all bit lines are biased at V
SS
. After all of the floating gates in the selected word are programmed, V
SS
(ground) is applied to line
35
and V
PP
is applied to those bit lines
32
-
0
through
32
-
7
containing bits that are to be erased, while the bit lines containing bits that are not to be erased remain biased at V
SS
.
There is a convenient consequence of this particular sequence of writing operations. Because all transistors in the selected word are initially programmed, they are in a nonconducting state when their control gates are grounded by applying V
SS
to line
35
. When V
PP
is applied to the selected bit lines, the floating gates of the selected transistors are erased into a conducting state and the common source line
35
is charged up. However, the voltage on the common source line is limited to Vfg-V
TN
, where Vfg is the floating gate potential and V
TN
is the threshold of the memory transistor when neutralized by extended exposure to ultraviolet light. This moderate voltage is too small to punch through the programmed transistors and so no current flows from the bit lines that are biased at V
PP
to those that are biased at V
SS
. It is this lack of direct current path that makes it possible to operate commercial EEPROMs from a single logic level power supply with all of the needed high voltages being generated on the chip by relatively small, low power charge pumps.
There are a couple of features of this prior art that limit its desirability for application in integrated circuit products in which only a small number of EEPROM bits are desired in a circuit that is primarily logic or a mixed signal pr
Caserza Steven F.
Flehr Hohbach Test Albritton & Herbert LLP
Zarabian A.
LandOfFree
Low voltage single CMOS electrically erasable read-only memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low voltage single CMOS electrically erasable read-only memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low voltage single CMOS electrically erasable read-only memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2461669