Low voltage single CMOS electrically erasable read-only memory

Static information storage and retrieval – Floating gate – Particular connection

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365149, G11C 1134

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active

059869313

ABSTRACT:
P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V.sub.PP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

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