Low voltage sensing circuit for non-volatile memory device

Details Low voltage sensing circuit for non-volatile memory device Low voltage sensing circuit for non-volatile memory device

2003-07-03

2004-08-10

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200

Reexamination Certificate

active

06775186

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to sense amplifier circuits used to detect the states of non-volatile memory cells in a non-volatile memory array.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) and flash erasable and programmable read only memories (flash EPROMs) are two types of non-volatile memory (NVM) devices. NVM cells typically comprise a sort of modified field-effect transistor (FET) that includes an electrically isolated floating gate (e.g., polycrystalline silicon or oxide-nitride-oxide (ONO)) for controlling conduction between source and drain regions of the EEPROM cell. A gate dielectric (bottom oxide) is formed between the floating gate and an underlying channel region between the source and drain regions. A control gate is provided adjacent to (e.g., above) the floating gate, and is separated from the floating gate by an inter-gate dielectric (top oxide). The data value stored by an EEPROM cell is determined by the amount of charge stored in the floating gate, which is controlled during program and erase operations by applying predetermined voltages across the floating gate. For example, during a program (write) operation, a net negative charge is transferred to and stored by the floating gate using a technique such as hot electron injection or Fowler-Nordheim (FN) tunneling. In this programmed state, the negative charge stored by the floating gate resists current flow between the source and drain regions of the memory cell when the control gate is asserted (i.e., pulled high). Conversely, an erase v operation transfers a neutral charge to the floating gate using FN tunneling. In the erased state, the neutral charge stored by the floating gate permits current flow between the source and drain regions of the memory cell when the control gate is asserted. NVM devices have an advantage over other volatile memories (e.g., static random access memory (SRAM) devices or dynamic RAM (DRAM) devices) in that the floating gate charge is stored essentially indefinitely (i.e., until a subsequent program/erase operation). That is, the charge stored by the floating gate of an NVM cell is retained even if power to the NVM device is disconnected, whereas data stored in volatile memory devices is lost when power is disconnected.
FIG. 1
is a simplified block diagram showing a conventional non-volatile memory (NVM) device
100
. NVM device
100
includes an array
110
of NVM cells
115
, and peripheral control circuitry located around array
110
including an input/output (I/O) control circuit
120
, a word line control circuit
130
, an optional address decoder
135
, a bit line control circuit
140
, a bit line (Y) decoder
145
, and a sense amplifier circuit
150
. NVM cells
115
are arranged in rows and columns such that the control gates of each row of NVM cells
115
are connected to an associated word line WL
0
through WL
7
, and each column of NVM cells
115
is connected to an associated pair of bit lines BL
0
through BL
8
. As indicated on the upper portion of
FIG. 1
, NVM device
100
also includes a reference NVM cell array
170
including several reference NVM cells. The reference NVM cells of reference NVM cell array
170
are utilized as discussed below.
Operation of NVM device
100
will now be briefly described with reference to FIG.
1
.
During program and erase operations, address data and an associated data word are respectively transmitted via I/O control circuit
120
to word line control circuit
130
(via optional address decoder
135
) and to bit line control circuit
140
. Word line control circuit
130
uses the address data to pass an appropriate program/erase voltage onto an associated word line (e.g., word line WL
0
), and bit line control circuit
140
then drives selected bit lines to transmit appropriate program/erase voltage needed to program selected NVM cells
115
of the selected row. According to one convention, the NVM cells
115
that are programmed store a logic “1” data value, and those NVM cells that remain erased (unprogrammed) store a logic “0” data value. During “flash” erase operations, the word lines and bit lines are maintained at an appropriate voltage level that causes all programmed NVM cells
115
to be erased. Those of ordinary skill in the art will recognize that the above explanation is greatly simplified, and that many variations in the described operations are possible.
NVM cells
115
are typically read (sensed) by comparing currents I
CELL[0]
-I
CELL[7]
passing through selected NVM cells (or voltages derived from the currents through the cells) to reference currents I
REF[0]
-I
REF[7]
(or voltages) derived from corresponding reference cells in reference NVM array
170
. In particular, during read operations, address data associated with selected data word is transmitted via I/O control circuit
120
to word line driver circuit
130
, which uses the address data to apply an appropriate read voltage on the associated word line (e.g., word line WL
1
), thereby causing the selected currents I
CELL[0]-I
CELL[7]
to pass from an associated word of the NMV cells onto, for example, bit lines BL
0
through BL
7
. The thus-read data word is then transmitted via Y-decoder
145
to sense amplifier circuit
150
, which compares the currents I
CELL[0]
-I
REF[7]
with corresponding reference currents. I
REP[0]
-I
REF[7]
. When the sensed current (or voltage) read from a particular NVM cell
115
is larger than the corresponding reference current (or voltage) generated by the reference NVM cell, the NVM cell
115
is considered to be erased. Conversely, if the sensed current (or voltage) is smaller than the corresponding reference current (or voltage), the read NVM cell
115
is considered to be programmed. Sense amplifier circuit,
150
then outputs detected data values D[
0
]-D[
7
] based on these comparisons to I/O control circuit
120
for transmission out of NVM device
100
.
FIG. 2
is a simplified circuit diagram showing a portion of conventional NVM circuit
100
that illustrates a conventional sensing scheme for determining the programmed/erased state of a selected NVM cell
115
-
1
. In particular,
FIG. 2
shows portions of NVM array
110
, bit line control circuit
140
, Y-decoder circuit
145
, sense amplifier circuit
150
, and reference array
170
. The portion of NVM array
110
shown in
FIG. 2
includes a selected NVM cell
115
-
1
, which is connected between bit lines BL
0
and BL
1
and is controlled by a word line voltage transmitted on word line WL
1
.
FIG. 2
also shows a portion of reference NVM array
170
including a reference NVM cell
115
-R
1
, which is connected between reference bit lines BLR
0
and BLR
1
and is controlled by a word line voltage transmitted on a word line WLR
1
(which may be the same word line WL
1
used to access selected NVM cell
115
-
1
).
Bit line control circuit
140
and Y-decoder circuit
145
, which are typically implemented by multiplexing circuits, are represented by a pass transistors
240
and
245
, respectively, which are controlled by control signals V
COL
—
SEL1
and V
COL
—
SEL
, respectively.
Sense amplifier circuit
150
includes a comparator (e.g., operational amplifier)
250
having a first (inverting) input terminal connected to a node N
1
, and a second (non-inverting) input terminal connected to a reference node RN
1
. Node N
1
is connected to the gate and drain terminals of a first PMOS transistor
252
, whose source terminal is connected to system voltage V
DD
. Node N
1
is also coupled to bit line BL
1
via a first NMOS clamp transistor
254
, whose conductance is controlled by a bias voltage V
BIAS
to prevent soft programming, and via pass transistor
245
of Y-decoder circuit
145
. Reference node RN
1
is connected to the gate and drain terminals of a second PMOS transistor
254
, whose source terminal is also connected to system voltage V
DD
. Reference node R

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