Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2000-02-29
2002-03-05
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S268000
Reexamination Certificate
active
06353363
ABSTRACT:
BACKGROUND OF THE INVENTION
Operational amplifiers in current electronic devices are provided with an output stage for driving additional devices connected to the amplifier in a particular application. To be suitable for broad application, it is preferable to provide such output stages with various characteristics, such as a relatively large and symmetrical output swing, preferably rail-to-rail. It is also desirable to have the output able to both source and sink a substantial amount of current in order to drive loads having a significant capacitive component. In addition, the output should dissipate a relatively low quiescent power to minimize power consumption when not driving such loads. Obviously, other characteristics such as stability, manufacturability, etc. are also important considerations.
Most prior art output stages capable of operating at one volt are push-pull class A output stages. In this case either the pull-up or the pull-down device is a current source, and the other device is configured in a common-source configuration. This results in a high level of power dissipation to drive large output loads.
To minimize power dissipation in the output stage, class AB stages are often used. Such stages have relatively low quiescent power dissipation, yet are capable of driving large amounts of current.
In bipolar technologies, low voltage push-pull output stages generally rely on controlling base current drive to the output transistors. Since bipolar transistors are current driven devices, the output current of the device can be controlled if the base is driven with a controlled current source. Since collector current is exponentially dependent upon the base-mitter voltage, a large change in output current can be realized for small changes in the base-emitter voltage. Thus, in a bipolar design capable of operating at one volt, a circuit may be designed to control the base current drive of the device, yet still achieve a high output current. However, in a CMOS circuit such techniques are not effective since the amount of output current is strictly a function of the amount of voltage between the gate and the source of the device (V
GS
).
CMOS push-pull output stages are generally designed such that one transistor is driven directly from the input of the output stage, and a complimentary transistor is driven by an output network. However, conventional CMOS output networks are problematic in that a conventional CMOS output network may or may not drive the complimentary transistor hard enough to create a symmetrical output. This problem is further increased at low voltages, such as at one volt.
Prior art
FIG. 1
is a schematic diagram of a conventional CMOS output stage
100
. The conventional output stage
100
includes P-channel transistor
102
and N-channel transistor
104
set in a push-pull configuration. In addition, output stage
100
includes P-channel transistor
106
and N-channel transistors
108
,
110
, and
112
, as well as current source
114
.
Conventional output stage
100
is an example of a IV CMOS push-pull output stage. Essentially, the drains of the P-channel transistor
102
and the N-channel transistor
104
are coupled together. In addition, the source of the P-channel transistor
102
is coupled to the positive power supply V
CC
, while the source of the N-channel transistor
104
is coupled to the negative power supply V
EE
. In this manner, the conventional output stage
100
achieves near rail-to-rail performance, until a load is placed at the output.
In order to provide negative drive capability, the conventional output stage
100
must be operated at a high quiescent current. Current source
114
, along with the area ratios of NMOS transistors
108
and
104
, set the maximum sink current capability of the output stage. The output sink current in NMOS
104
is controlled by replica PMOS transistor
106
, which controls the bias to NMOS transistors
110
and
112
. NMOS
110
then modulates the bias to output NMOS
104
. The output drive capability of circuit
100
is not symmetrical, since the drain current in PMOS
102
is limited only by its V
GS
, while the NMOS
104
can only deliver I
114
((W/L
104
)/(W/L
108
)). This limits the type of applications that will function properly with output stage
100
.
In view of the foregoing, what is needed is an output stage that provides near rail-to-rail performance, which does not require a high quiescent current to provide negative drive capability. Moreover, the output stage should be capable of operating from low supply voltages, such as slightly more than a single V
GS
voltage.
SUMMARY OF THE INVENTION
The present invention address this need by providing an output stage that provides essentially rail-to-rail performance, and operates from supply voltages down to slightly more than a single V
GS
voltage. In one embodiment, an output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage is disclosed. The output stage includes a first field effect device having a first drain, a first gate, and a first source coupled to a power supply V
CC
. The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of V
EE
. Further, the second drain is coupled to the first drain. Also included in the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a product of a current in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.
In another embodiment, a method for providing an output signal from an output stage of a low voltage amplifier capable of providing a substantially rail-to-rail output voltage is disclosed. The method comprises providing an input signal to a first field effect device having a first drain, a first gate, and a first source coupled to a power supply V
CC
. Next, a second complimentary field effect device is driven utilizing an output sink network such that the product of the current in the first field effect device and the current in the second field effect device is essentially equal to a predetermined constant during operation of the amplifier.
In yet another embodiment, an application specific integrated circuit (ASIC) having an output stage for a low voltage operational amplifier is disclosed. The ASIC includes a first field effect device having a first drain, a first gate, and a first source coupled to a power supply V
CC
. The ASIC further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of V
EE
. Further, the second drain is coupled to the first drain. Also included in the ASIC is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that the product of the current in the first field effect device and the current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.
An operational amplifier output stage is disclosed in a further embodiment of the present invention. The operational amplifier output stage includes a push-pull output network that receives a first input signal and a second input signal, the first input signal being provided by an input signal V
IN
. Also included in the operational amplifier output stage is an output sink network that provides the second input signal to the push-pull output network.
Finally, an operational amplifier suitable for operating on low input voltage and capable of providing a substantially symmetrical rail-to-rail output voltage is disclosed. The operational amplifier includes an input stage and an output stage coupled to
Choe Henry
Gain Technology Corporation
Oppenheimer Wolff & Donnelly
Pascal Robert
LandOfFree
Low voltage rail-to-rail CMOS output stage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low voltage rail-to-rail CMOS output stage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low voltage rail-to-rail CMOS output stage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2851940