Low-voltage punch-through transient suppressor employing a dual-

Details Low-voltage punch-through transient suppressor employing a dual- Low-voltage punch-through transient suppressor employing a dual-

1998-03-16

2000-01-18

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Punchthrough structure device

257361, 257362, H01L 2900

Patent

active

060159995

ABSTRACT:
A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm.sup.-3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p- layer should be between about 0.5E14 cm.sup.-3 and about 1.OE17 cm.sup.-3. The junction depth of the fourth (n+) region should be greater than about 0.3 .mu.m. The thickness of the third (p+) region should be between about 0.3 .mu.m and about 2.0 .mu.m, and the thickness of the second (p-) region should be between about 0.5 .mu.m and about 5.0 .mu.m.

REFERENCES:
patent: 4017882 (1977-04-01), Kannam
patent: 4405932 (1983-09-01), Ishic
patent: 4602267 (1986-07-01), Shirato
patent: 5528064 (1996-06-01), Thiel

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