Active solid-state devices (e.g. – transistors – solid-state diode – Punchthrough structure device
Reexamination Certificate
2001-07-11
2003-07-29
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Punchthrough structure device
C257S361000, C257S653000
Reexamination Certificate
active
06600204
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices. More particularly, the present invention relates to low-voltage punch-through bi-directional transient-voltage suppression devices having significant protection against surface breakdown.
BACKGROUND OF THE INVENTION
Electronic circuits that are designed to operate at low supply voltages are common in the electronics industry. Current trends toward a reduction in circuit operating voltage dictate a corresponding reduction in the maximum voltage that the circuitry can withstand without incurring damage. Such damage can arise from overvoltage conditions caused by electrostatic discharge, inductively coupled spikes, or other transient conditions. Hence, demand presently exists for transient-voltage suppressors having low breakdown voltages, for example, voltages in the 3-6 volt range.
One traditional device for overvoltage protection is the reversed biased p+n+ Zener diode. These devices perform well at higher voltages, but run into problems, specifically large leakage currents and high capacitance, at low breakdown voltages. For example, as breakdown voltages are reduced from 12 volts to 6.8 volts, leakage currents for these devices dramatically increase from about 1 &mgr;A to about 1 mA.
In response to these problems, low-voltage punch-through transient-voltage suppressors have been developed. Specifically, as seen in U.S. Pat. No. 5,880,511 to Semtech Corporation, the entire disclosure of which is hereby incorporated by reference, a transient suppressor device is described which comprises a n+p−p+n+ punch-through diode. Such devices can have low breakdown voltages, while having leakage and capacitance characteristics superior to those of certain prior-art transient suppressors. In contrast to, for example, Zener diodes, which provide overvoltage protection based on avalanche breakdown (i.e., breakdown caused by impact ionization that leads to carrier multiplication), these devices provide overvoltage protection as a result of punch-through. (Punch-through can be readily illustrated with reference to a transistor. For a transistor, punch-through occurs when a depletion region becomes as wide as the base of the transistor. Typically, punch-through occurs in a bipolar transistor where the depletion region of the collector junction of the transistor reaches the emitter junction on the opposite side of the base layer at voltages below the avalanche breakdown voltage of the collector junction.) The n+p−p+n+ devices of U.S. Pat. No. 5,880,511 are also claimed to be superior to other transient-voltage suppression devices, specifically n+pn+ uniform-base punch-through devices, which are claimed to suffer from poor clamping characteristics at high currents. Unfortunately, n+p−p+n+ devices, such as those described in U.S. Pat. No. 5,880,511 have current-voltage characteristics that are not symmetric. As a result, in order to make bi-directional transient-voltage suppressors, Semtech proposes a circuit of two of their transient-voltage suppressors in anti-parallel. Obviously, this arrangement adds expense in that it requires more than one device to achieve its intended function.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, a bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown. For example, the integral preferably ranges from 2×10
12
to 1×10
13
cm
−2
Preferably, the upper and lower layers of this device have higher peak net doping concentrations than the middle layer. More preferably, the middle layer has a net doping concentration that is highest at a midpoint between the junctions, and the doping profile along a line normal to the lower, middle and upper layers is such that the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side of the centerplane, within said lower, middle and upper layers.
The bi-directional transient voltage suppression device preferably comprises a p++ semiconductor substrate, a first p+ epitaxial layer adjacent the p++ substrate, an n epitaxial layer adjacent the first epitaxial p+ layer, and a second p+ epitaxial layer adjacent the n epitaxial layer. Moreover, the peak net doping concentration of each of the lower and upper p+ epitaxial layers preferably ranges from 5 to 20 times the peak net doping concentration of the n epitaxial layer.
This device is preferably a silicon device, the p-type conductivity is preferably provided by a boron dopant, and the n-type conductivity is preferably provided by a phosphorous dopant. The oxide layer is preferably a thermally grown oxide layer, and is more preferably thermally grown under wet conditions.
According to another embodiment of the invention, a method of forming a bi-directional transient voltage suppression device is provided. The method comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity over the substrate; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer, such that the lower layer and the middle layer form a lower p-n junction; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer, such that the middle layer and the upper layer form an upper p-n junction; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions, increasing the distance between the upper and lower junctions at the walls. The above procedures are conducted such that an integral of the net doping concentration of the middle layer, when taken over the distance between the upper and lower junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
The semiconductor is preferably a silicon semiconductor, the p-type conductivity is preferably provided by a boron dopant, and the n-type conductivity is preferably provided by a phosphorous dopant. The step of forming the oxide layer is preferably a wet thermal growth step. In some instances, the device is subjected to a compensation diffusion step after forming the oxide layer.
One advantage of the present invention is that a low-voltage bi-directional transient-voltage suppressor is provided that has a low leakage current.
A further advantage of the present invention is that a low-voltage bi-directional transient-voltage suppressor is provided that has a lower capacitance than the Zener transient-voltage suppression device with the same breakdown voltage.
Yet another advantage of the present invention is that a low-voltage bi-directional
Einthoven Willem G.
Ginty Anthony
Walsh Aidan
Bonham, Esq. David
General Semiconductor Inc.
Mansfield Esq. Heather L.
Mayer Fortkort & Williams PC
Prenty Mark V.
LandOfFree
Low-voltage punch-through bi-directional transient-voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low-voltage punch-through bi-directional transient-voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-voltage punch-through bi-directional transient-voltage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3104594