Active solid-state devices (e.g. – transistors – solid-state diode – Punchthrough structure device
Reexamination Certificate
2001-05-22
2002-12-03
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Punchthrough structure device
C257S361000
Reexamination Certificate
active
06489660
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices. More particularly, the present invention relates to low-voltage punch-through bi-directional transient-voltage suppression devices having symmetric current-voltage characteristics.
BACKGROUND OF THE INVENTION
Electronic circuits that are designed to operate at low supply voltages are common in the electronics industry. Current trends toward a reduction in circuit operating voltage dictate a corresponding reduction in the maximum voltage that the circuitry can withstand without incurring damage. Such damage can arise from overvoltage conditions caused by electrostatic discharge, inductively coupled spikes, or other transient conditions. Hence, demand presently exists for transient-voltage suppressors having low breakdown voltages, for example, voltages in the 3-6 volt range.
One traditional device for overvoltage protection is the reversed biased p+n+ Zener diode. These devices perform well at higher voltages, but run into problems, specifically large leakage currents and high capacitance, at low breakdown voltages. For example, as breakdown voltages are reduced from 12 volts to 6.8 volts, leakage currents for these devices dramatically increase from about 1 &mgr;A to about 1 mA.
In response to these problems, low-voltage punch-through transient-voltage suppressors have been developed. Specifically, as seen in U.S. Pat. No. 5,880,511 to Semtech Corporation, the entire disclosure of which is hereby incorporated by reference, a transient suppressor device is described which comprises a n+p−p+n+ punch-through diode. Such devices can have low breakdown voltages, while having leakage and capacitance characteristics superior to those of certain prior-art transient suppressors. In contrast to, for example, Zener diodes, which provide overvoltage protection based on avalanche breakdown (i.e., breakdown caused by impact ionization that leads to carrier multiplication), these devices provide overvoltage protection as a result of punch-through. (Punch-through can be readily illustrated with reference to a transistor. For a transistor, punch-through occurs when a depletion region becomes as wide as the base of the transistor. Typically, punch-through occurs in a bipolar transistor where the depletion region of the collector junction of the transistor reaches the emitter junction on the opposite side of the base layer at voltages below the avalanche breakdown voltage of the collector junction.) The n+p−p+n+ devices of U.S. Pat. No. 5,880,511 are also claimed to be superior to other transient-voltage suppression devices, specifically n+pn+ uniform-base punch-through devices, which are claimed to suffer from poor clamping characteristics at high currents. Unfortunately, n+p−p+n+ devices, such as those described in U.S. Pat. No. 5,880,511 have current-voltage characteristics that are not symmetric. As a result, in order to make bi-directional transient-voltage suppressors, Semtech proposes a circuit of two of their transient-voltage suppressors in anti-parallel. Obviously, this arrangement adds expense in that it requires more than one device to achieve its intended function.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, a bi-directional transient voltage suppression device with symmetric current-voltage characteristics is provided. The device comprises: (a) a lower semiconductor layer of first conductivity type; (b) an upper semiconductor layer of first conductivity type; and (c) a middle semiconductor layer adjacent to and disposed between the lower and upper layers. In this device, the middle layer has a second conductivity type opposite the first conductivity type, such that upper and lower p-n junctions are formed. Moreover, the middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the lower, middle and upper layers, the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side of the centerplane. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
Preferably, the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity. Phosphorous is preferably used as an n-type dopant, and boron is used as a p-type dopant. More preferably, the bi-directional transient voltage suppression device comprises a p++ semiconductor substrate, a first epitaxial p+ layer deposited on the p++ substrate, an epitaxial n layer deposited on the first epitaxial p+ layer, and a second epitaxial p+ layer deposited on the epitaxial n layer. A p++ ohmic contact is typically formed at an upper surface of the second epitaxial p+ layer.
It is also preferred that the peak net doping concentration of each of the first and second epitaxial p+ layers ranges from 5 to 20 times the peak net doping concentration of the epitaxial n layer. Preferably, the peak net doping concentration of the epitaxial n layer ranges from 2×10
16
cm
−3
to 2×10
17
cm
−3
, and the peak net doping concentration of the first and second epitaxial p+ layers range from 2×10
17
cm
−3
to 2×10
18
cm
−3
. The integral of the middle layer net doping concentration taken over the distance between the junctions preferably ranges from 2×10
12
to 1×10
13
cm
−2
. The preferred distance between the upper and lower junctions ranges from 0.2 to 1.5 microns.
The first and second epitaxial p+ layers are preferably sufficiently thick to more evenly distribute electrical current throughout the device. It is also preferred that the minority lifetime, punch through breakdown voltage, and theoretical avalanche breakdown voltage be selected so as to produce a Vceo (i.e., collector-emitter voltage, open base) having negative dynamic resistance that compensates for at least a portion of the positive dynamic resistance of the device in the on state.
In contrast to the above, in certain embodiments of the invention, the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity. Within these embodiments, the bi-directional transient voltage suppression device preferably comprises an n++ substrate, a first epitaxial n+ layer deposited on the n++ substrate, an epitaxial p layer deposited on the first epitaxial n+ layer, and a second epitaxial n+ layer deposited on the epitaxial p layer.
According to further embodiment of the invention, a method of making a bi-directional transient voltage suppression device is provided. The method comprises the following: (a) providing a semiconductor substrate of a first conductivity type; (b) depositing a lower epitaxial layer of the first conductivity type on the substrate; (c) depositing a middle epitaxial layer having a second conductivity type opposite the first conductivity type on the lower epitaxial layer, such that the lower layer and the middle layer form a lower p-n junction; (d) depositing an upper epitaxial layer of the first conductivity type on the middle epitaxial layer, such that the middle layer and the upper layer form an upper p-n junction; and (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer. The above procedures are conducted such that: (a) the middle layer is provided with a net carrier concentration that is highest at a midpoint between the junctions, (b) a doping profile along a line normal to the lower, middle and upper epitaxial layers is established in which, within the lower, middle and upper layers, the doping profile on one side of a centerplane
Einthoven Willem G.
Eng Jack
Garbis Danny
Horsman Gary
LaTerza Lawrence
Bonham, Esq. David B.
Elms Richard
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Smith Bradley
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