Low voltage one transistor flash EEPROM cell using Fowler-Nordhe

Static information storage and retrieval – Floating gate – Particular biasing

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36518501, 36518529, 36518505, 365218, 365200, G11C 700

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055879470

ABSTRACT:
A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

REFERENCES:
patent: 3593037 (1971-07-01), Hoff, Jr.
patent: 3660819 (1972-05-01), Frohman-Bentchkowsky
patent: 3699646 (1972-10-01), Vadasz
patent: 3728695 (1973-04-01), Frohman-Bentchkowsky
patent: 3755721 (1973-08-01), Frohman-Bentchkowsky
patent: 3810127 (1974-05-01), Hoff, Jr.
patent: 3825442 (1974-07-01), Moore
patent: 3825946 (1974-07-01), Frohman-Bentchkowsky
patent: 3876887 (1975-04-01), Reed
patent: 3891190 (1975-06-01), Vadasz
patent: 3918149 (1975-11-01), Roberts
patent: 3919711 (1975-11-01), Chou
patent: 3975671 (1976-08-01), Stoll
patent: 3978459 (1976-09-01), Koo
patent: 3984822 (1976-10-01), Simko et al.
patent: 3996657 (1976-12-01), Simko et al.
patent: 3997381 (1976-12-01), Wanlass
patent: 4013484 (1977-03-01), Boleky et al.
patent: 4013489 (1977-03-01), Oldham
patent: 4026733 (1977-05-01), Owen, III et al.
patent: 4026740 (1977-05-01), Owen, III et al.
patent: 4052229 (1977-10-01), Pashley
patent: 4087795 (1978-05-01), Rossler
patent: 4092661 (1978-05-01), Watrous, Jr.
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4099196 (1978-07-01), Simko
patent: 4103189 (1978-08-01), Perlegos et al.
patent: 4114255 (1978-09-01), Salsbury et al.
patent: 4119995 (1978-10-01), Simko
patent: 4122544 (1978-10-01), McElroy
patent: 4153933 (1979-05-01), Blume, Jr. et al.
patent: 4176258 (1979-11-01), Jackson
patent: 4180826 (1979-12-01), Shappir
patent: 4203158 (1980-05-01), Frohman-Bentchowsky et al.
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4231811 (1980-11-01), Somekh et al.
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4257056 (1981-03-01), Shum
patent: 4266283 (1981-05-01), Perlegos et al.
patent: 4267632 (1981-05-01), Shappir
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 4451748 (1984-05-01), Amrany
patent: 4460982 (1984-07-01), Gee et al.
patent: 4527180 (1985-07-01), Oto
patent: 4551910 (1985-11-01), Patterson
patent: 4571709 (1986-02-01), Skupnjak et al.
patent: 4613886 (1986-09-01), Chwang
patent: 4642798 (1987-02-01), Rao
patent: 4654958 (1987-04-01), Baerg et al.
patent: 4658084 (1987-08-01), Canepa
patent: 4658160 (1987-04-01), Young
patent: 4698787 (1987-10-01), Murkherjee et al.
patent: 4780424 (1988-10-01), Holler et al.
patent: 4784965 (1988-11-01), Woo et al.
patent: 4804637 (1989-02-01), Smayling et al.
patent: 4814286 (1989-03-01), Tam
patent: 4841482 (1989-06-01), Kreifels et al.
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 4868619 (1989-09-01), Murkherjee et al.
patent: 4875188 (1989-10-01), Jungroth
patent: 4875191 (1989-10-01), Mulder et al.
patent: 4930098 (1990-05-01), Allen
patent: 4949140 (1990-08-01), Tam
patent: 5039941 (1990-10-01), Tzeng
patent: 5053990 (1991-08-01), Castro
patent: 5065364 (1991-10-01), Kreifels et al.
patent: 5075245 (1991-11-01), Atwood et al.
patent: 5091332 (1992-02-01), Bohr et al.
patent: 5104819 (1992-04-01), Freiberger et al.
patent: 5109187 (1992-04-01), Gulianai
patent: 5120671 (1992-06-01), Tang et al.
patent: 5136544 (1992-08-01), Rozman et al.
patent: 5142495 (1992-08-01), Canepa
patent: 5237535 (1993-08-01), Mielke et al.
patent: 5278440 (1994-01-01), Shimoji
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5311049 (1994-05-01), Tsuruta
patent: 5357463 (1994-10-01), Kinney
patent: 5408431 (1995-04-01), Challa
patent: 5424991 (1995-06-01), Hu
patent: 5424993 (1995-06-01), Lee et al.
patent: 5428578 (1995-06-01), Kaya et al.
patent: 5483485 (1996-01-01), Maruyama
patent: 5508959 (1996-04-01), Lee et al.
Sameer Haddad et al., An Investigation of Erase-Mode Dependent Hole Trapping in Flash EEPROM Memory Cell, IEEE Electron Device Letters, vol. 11, No. 11, Nov. 1990, pp. 514-516.
Samachisa et al., A 128K Flash EEPROM Using Double-Polysilicon Technology, IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 676-682.
Scheibe, A. and Krauss, W., A Two-Transistor SIMOS EAROM Cell, IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1990, pp. 353-357.
Konemann et al., Built-In Test for Complex Digital Integrated Circuits, IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1990, p. 315.
Giebel, B., An 8K EEPROM Using the SIMOS Storage Cell, IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980, pp. 311-314.
Kynett et al., A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory, IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1259-1263.
Guterman, et al., An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure, IEEE Journal of Solid-State Circuits, vol. SC-14, No. 2, Apr. 1979, pp. 498-508.
Kahng, D. and Sze, S. M., A Floating Gate and Its Application to Memory Devices, May 16, 1967, pp. 1288-1295.
Hijiya et al., Session IX: Nonvolatile Memories, 1982 IEEE International Solid-State Circuits Conference, pp. 116-117.
Muller et al., A 8192-Bit Electrically Alterable ROM Employing a One-Transistor Cell with Floating Gate, IEEE Journal of Solid-State Circuits, vol. SC-12, No. 4, Oct. 1977, pp. 507-514.
Takeda et al., Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation, IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1992, pp. 611-617.
Dill et al., Session IV: Semiconductor Memories, WPM 4.4: Anomalous Behavior in Stacked-Gate MOS Tetrodes, 1969 IEEE International Solid-State Circuits Conference, pp. 44-45.
Verma, G. and Mielke, Neal, Reliability Performance of ETOX based Flash Memories, 1988 IEEE/IRPS, pp. 158-166.
Keeney et al., Complete Transient Simulation of Flash EEPROM Devices, IEEE Transactions on Electron Devices, vol. 39, No. 12, Dec. 1992, pp. 2750-2756.
Jenq et al., Properties of Thin Oxnitride Films Used as Floating-Gate Tunneling Dielectrics, IEDM 82, 30.9, pp. 811-812.
Sternheim et al., Properties of Thermal Oxide Grown on Phosphorus In Situ Doped Polysilicon, Journale of the Electrochemical Society: Solid-State Science and.
Maseo Kurlyama et al.--A 5V-Only 0.6.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, 1992 IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 152-153, Feb. 20, 1992.
Yeargain, J., Kuo, C., "A High Density Floating-Gate EEPROM Cell", IEDM 1981, pp. 24-27.
Kuo, C. et al., "Tham 9.1: A Sub 100ns 32K EEPROM", 1982 IEEE International Solid-State Circuits Conference, pp. 106-107, p. 301.

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