Low voltage one transistor flash EEPROM cell using fowler-nordhe

Details Low voltage one transistor flash EEPROM cell using fowler-nordhe Low voltage one transistor flash EEPROM cell using fowler-nordhe

1997-11-17

1999-08-17

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 3651853, 36518526, 36518524, G11C 700, H01L 2978

Patent

active

059403250

ABSTRACT:
A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

REFERENCES:
patent: 5574684 (1996-11-01), Tomoeda
patent: 5576992 (1996-11-01), Mehrad
patent: 5596530 (1997-01-01), Lin et al.
patent: 5615147 (1997-03-01), Chang et al.
patent: 5687120 (1997-11-01), Chang et al.
patent: 5748538 (1998-05-01), Lee et al.
patent: 5844847 (1998-12-01), Kobatake
patent: 5856945 (1999-01-01), Lee et al.

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