Low voltage nonvolatile memory device

Details Low voltage nonvolatile memory device Low voltage nonvolatile memory device

1980-10-01

1982-10-05

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 13, 357 54, 357 89, 365184, H01L 2978, H01L 2990, H01L 2934, G11C 1134

Patent

active

043530834

ABSTRACT:
A low voltage write, avalanche breakdown, nonvolatile MNOSFET memory device. The device is preferably an n-channel enhancement mode, split-gate or trigate structure having a first, relatively highly doped p+ channel region and a second, underlying p-region. The p+ region is coextensive with the thin, memory oxide structure. The binary state of the device is selected by applying a low voltage (e.g., +12v) to the gate and simultaneously applying a suitable voltage to the source and/or drain to induce avalanche breakdown in the channel, or not, to write the device to a "1" state or maintain the device in its original "0" state.

REFERENCES:
patent: 3719866 (1973-03-01), Naber et al.
patent: 4017888 (1977-04-01), Christie et al.
patent: 4019198 (1977-04-01), Endo et al.
patent: 4068217 (1978-01-01), Arnett et al.
patent: 4101921 (1978-07-01), Shimada et al.
patent: 4151538 (1979-04-01), Polinsky et al.
patent: 4307411 (1981-12-01), Carnes et al.

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