Low voltage non-volatile memory cell

Details Low voltage non-volatile memory cell Low voltage non-volatile memory cell

2005-04-19

2005-04-19

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185240, C365S185280

Reexamination Certificate

active

06882571

ABSTRACT:
A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

REFERENCES:
patent: 5341016 (1994-08-01), Prall et al.
patent: 5627400 (1997-05-01), Koga
patent: 5656528 (1997-08-01), Wahlstrom
patent: 5821160 (1998-10-01), Rodriguez et al.
patent: 5972756 (1999-10-01), Kono et al.
patent: 6235574 (2001-05-01), Tobben et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6482698 (2002-11-01), Peschiaroli et al.
patent: 6495424 (2002-12-01), Kunikiyo
patent: 6496416 (2002-12-01), Look
patent: 6627928 (2003-09-01), Peschiaroli et al.
patent: 6671205 (2003-12-01), Look
patent: 20020022326 (2002-02-01), Kunikiyo
patent: 360009160 (1985-01-01), None
patent: 363079377 (1988-04-01), None
patent: 406163906 (1994-06-01), None
patent: 406232389 (1994-08-01), None
patent: 408264660 (1996-10-01), None
patent: 2000077356 (2000-03-01), None
patent: 02000082803 (2000-03-01), None
“Boron Diffusion And Penetration In Ultrathin Oxide With Poly-Si Gate”; Cao et al.; IEEE Electron Device Letters; vol. 19; No. 8; Aug. 1998; pp. 291-293.
Aoyama et al.; “Flat-band Voltage Shifts In P-MOS Devices Caused By Carrier Activation In P+-Polycrystaline Silicon and Boron Penetration”; 1997 IEEE; pp. 26.1.1-26.1.4.
Alavi et al.; “A PROM Element Based On Salicide Agglomeration Of Poly Fuses In A CMOS Logic Process”; 1997 IEEE; pp. 34.3.1-34.3.4.
Jang et al.; “Effects Of Thermal Processes After Silicidation On The Performance Of TiSi2/Polysilicon Gate Device”; IEEE Transactions On Electron Devices; vol. 46; No. 12; Dec. 1999; pp. 2353-2356.
Lasky et al.; “Comparison Of Transformation To Low-Resistivity Phase And Agglomeration Of TiSi2and CoSi2”; IEEE Transaction On Electron Devices; vol. 38; No. 2; Feb. 1991; pp. 262-269.
Kalnitsky et al.; “CoSi2Integrated Fuses On Poly Silicon For Low Voltage 0.18 um CMOS Application”; 1999 IEEE; 4 pages.

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