Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2001-07-03
2003-03-11
Lee, Benny (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C330S288000
Reexamination Certificate
active
06531923
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to bias circuits, and more particularly, to such a bias circuit for establishing bias voltages suitable for biasing current sources.
2. Related Art
FIG. 7A
is a circuit diagram of a known, simple current mirror including an input diode M
31
and a current source Field Effect Transistor (FET) M
32
. The simple current mirror simply replicates (perhaps proportionately) the input diode current I
IN2
as an output current I
OUT2
. While this circuit is simple, a problem can arise because the drain-source voltage of FET M
31
is not necessarily equal to the drain-source voltage of FET M
32
. This causes the current I
OUT2
flowing through FET M
32
to be different from the current I
IN2
flowing through diode M
31
. This is especially the case for devices having relatively short channels (also referred to as short-channel devices), such as sub-micron devices.
FIG. 7B
is a circuit diagram of a known cascode current mirror used to solve the above-mentioned problem. The cascode current mirror keeps the drain-source voltages of both FETs M
33
and M
34
the same. However, the voltage at the top of FET M
35
(that is, on the drain of FET M
35
) can be relatively high, perhaps more than ½ the power supply voltage VDD. Therefore, changes in voltage VDD cause significantly larger corresponding changes in input current. All of this amounts to a circuit having the disadvantage of very high power supply sensitivity (that is, an undesired sensitivity to power supply voltage variations).
FIG. 7C
is a circuit diagram of a self-biased current mirror used to overcome the above-mentioned power supply sensitivity. The current through M
42
is basically the voltage across diode M
41
divided by the resistance of R
10
. This current can then be mirrored to the output through the p-type Metal Oxide Semiconductor (PMOS) devices M
44
-M
46
. Such self-biased reference circuits also need a start-up circuit to ensure they attain a proper operating state. The circuit of
FIG. 7C
tends to have the disadvantage that currents in the circuit tend to vary in undesired or wrong directions over process and temperature variations. Also, the input current can not be conveniently adjusted.
FIG. 7D
is a bandgap circuit using parasitic bipolar transistors in a Complementary Metal Oxide Semiconductor (CMOS) substrate to create controlled reference voltages. One voltage goes as delta-VBE and the other goes as KT/q multiplied up. Since the temperature coefficients of each of these voltages go in opposite directions, a temperature independent voltage can be achieved. However, bandgap references tend to require a start-up circuit to ensure proper operation thereof. Also, the bandgap circuit is not space-efficient because of the large area required by the PNP transistors used in the circuit. PNP transistors are lateral (not vertical) devices with poor beta and very low maximum current.
There is a need therefore for an improved bias circuit that overcomes all of the above-mentioned shortcomings and disadvantages of known circuits.
SUMMARY OF THE INVENTION
Summary
The present invention overcomes the above-mentioned shortcomings and disadvantages of know circuits. The present invention is directed to a low voltage input current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the bias circuit. In one embodiment, the circuit includes an input stage adapted to establish a first bias voltage at the input terminal in response to the input current. The circuit further includes a current stage adapted to produce a bias current and a main mirror current each proportional to the input current in response to the first bias voltage and a second bias voltage. The circuit further includes a feedback stage adapted to produce a feedback current proportional to the input current in response to the bias current and the main mirror current. The circuit further includes a reference bias stage adapted to establish the second bias voltage in response to the feedback current from the feedback stage, whereby the first and second bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.
Another aspect of the present invention is a method of establishing a plurality of bias voltages suitable for biasing current sources from an input current supplied to a bias circuit. The method comprises the steps of (a) supplying an input current, (b) establishing a first bias voltage in response to the input current, (c) producing a bias current proportional to the input current in response to the first bias voltage and a second bias voltage, (d) producing a main mirror current proportional to the input current in response to the first bias voltage and the second bias voltage, (e) producing a feedback current proportional to the input current in response to the bias current and the main mirror current, and (f) establishing the second bias voltage in response to the feedback current, whereby the first and second bias voltages track the input current over variations in at least one of a temperature and a power supply voltage of the bias circuit.
Features and Advantages
A. The bias circuit of the present invention is more space-efficient, physically smaller, and less complex than known bandgap reference circuits.
B. The bias circuit of the present invention exhibits much lower thermal noise than the bandgap reference circuit, for example, when an external capacitor to ground is used across an input stage of the bias circuit.
C. The bias circuit of the present invention uses an external resistor to set an input current to the bias circuit, allowing for a trade-off between performance and power.
D. The bias circuit of the present invention includes a shut-down stage or mechanism to selectively turn-off an input current to the bias circuit.
E. The bias circuit of the present invention generates reference voltages compatible with complementary types of logic, such as NMOS and PMOS reference circuits.
F. The bias circuit of the present invention has low power supply sensitivity.
G. The bias circuit of the present invention produces reference currents and bias voltages that vary only slightly with process, temperature and power supply voltage. These variations tend to partially compensate gain variations, without increasing distortion.
REFERENCES:
patent: 4518869 (1985-05-01), Herold
patent: 4983929 (1991-01-01), Real et al.
patent: 5164614 (1992-11-01), Maekawa
patent: 5686824 (1997-11-01), Rapp
patent: 5739719 (1998-04-01), Tanabe et al.
patent: 5812024 (1998-09-01), Mastrocola
patent: 5892394 (1999-04-01), Wu
patent: 6025792 (2000-02-01), Smith
patent: 0 356 020 (1990-02-01), None
patent: 0 846 997 (1998-06-01), None
International Search Report issued Feb. 11, 2002 for Appln. No. PCT/US01/21033, 7 pages.
Broadcom Corporation
Choe Henry
Lee Benny
Sterne Kessler Goldstein & Fox P.L.L.C.
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