Low voltage high frequency ring oscillator for controling phase-

Oscillators – Ring oscillators

Patent

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Details

331 55, 331177R, 331172, H03B 524

Patent

active

056358776

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to an oscillator, and more particularly to a ring oscillator.


BACKGROUND TO THE INVENTION

New manufacturing processes and new applications are forcing power supplies to lower voltages (3.3 v now, with 2.4 v and 1.5 v being expected soon). Advanced Phase-Locked Loops require stable oscillators which may be varied in frequency by a control signal.
To help achieve frequency stability, oscillators integrated into a noisy VLSI environment often use a regulator to generate a quiet power supply. This usually has to be at an even lower voltage than the normal power supply.
There is thus a desire to provide oscillators which can work at these very low supply voltages and still produce high quality, high frequency output signals.


SUMMARY OF THE INVENTION

According to the present invention there is provided an oscillator comprising two oscillator rings, where each oscillator ring comprises the same number of oscillator stages. Each stage has a single input and a single output and is operable to provide at the output an output signal which is phase-shifted by a controllable amount relative to an input signal provided at the input. Each stage has a current source arranged to receive a control signal to adjust the phase-shift, and the input of each stage is connected to receive the output of a preceding stage. The oscillator further comprises synchronization circuitry connected between the outputs of two aligned stages in the coupled oscillator rings and operable to maintain the outputs 180.degree. apart in phase.
Where there is an even number of stages in each ring the rings are coupled by connection of the output of a last stage in each ring to the input of a first stage in the other ring.
Preferably there is synchronization circuitry between each set of two aligned stages.
The synchronization circuitry can comprise first and second cross-coupled transistors acting in a feedback arrangement between the outputs.
Each stage can comprise first and second transistors, wherein the first transistor has a controllable path connected between an output node and a reference voltage and a control node acting as an input node to the stage. The second transistor has a controllable path connected between the output node and the reference voltage and a control node connected to the output node, the current source being connected to the output node.
For transistors of the same length, the width of the first transistor can be set to m times the width of the second transistor where m>1 to determine the d.c. gain of the stage.
The ratio m determines the shape of the waveform output by the oscillator. The higher the value of m, the more the waveform moves away from a sinusoid to a trapezoidal or sawtooth waveform. Preferably, the value of m is selected to produce a trapezoidal or sawtooth waveform. For a three stage oscillator a value of m close to 2 produces a substantially sinusoidal output. The present invention preferably uses a minimum value of m=2.5 for a three stage ring to produce a trapezoidal or sawtooth output.
The maximum value of m is limited by practical considerations, particularly layout considerations. A practical maximum value for m is likely to be about 10. A trapezoidal or sawtooth waveform has a more stable amplitude over a wide range of frequencies and so can more readily be converted to CMOS levels.
The first and second transistors can be n-channel field effect devices having a gate as the control node and the source-drain path as the controllable path. As the transistors are of the same type, process variations affect the transistors in the same manner. The maximum frequency of operation is limited only by the ratio of gain to gate capacitance.
The current source can comprise a p-channel transistor gated by a control voltage.
The first transistor is preferably operated in its saturation region.
The current sources of each stage can either be controlled by a common control signal or by respective different control signals.
When implemented with each stage bein

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Bennett et al., "Sub-Nanosecond Bipolar LSI," 1st I.E.E. European Solid State Circuits Conference, London, GB, pp. 34-35, 1975.
IBM Technical Disclosure Bulletin, 32:(12), pp. 149-151, 1993.
Kumar, U. and S. P. Suri, "A simple digital 2" frequency multiplier," Int. J. Electronics 48:(1), pp. 43-45, 1980.
McGahee, T., "Pulse-frequency doubler requires no adjustment," Electronics 48:(8), p. 149, Apr. 1975.
Ware, et al., "THPM 14.1: A 200 MHz CMOS Phase-Locked Loop With Dual Phase Detectors," IEEE International Solid-State Circuits Conference, New York, USA, pp. 192-193 and 338, Feb. 1989.
IBM Technical Disclosure Bulletin 31(2):154-156, 1988, (Jul. 1988).

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