Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1995-05-26
1996-07-30
Gaffin, Jeffrey A.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361111, 257355, H02H 904
Patent
active
055418015
ABSTRACT:
An electrostatic discharge (ESD) protection circuit for eliminating the stress of electrostatic discharge and preventing destruction of an internal semiconductor circuit. A first low-voltage gate trigger silicon controlled rectifier anode and anode gate, a second low-voltage gate trigger silicon controlled rectifier anode gate and a third low-voltage gate trigger silicon controlled rectifier anode gate are each coupled to a reference high potential. A second low-voltage gate trigger silicon controlled rectifier cathode and cathode gate and a third low-voltage gate trigger silicon controlled rectifier anode are each coupled to a reference low potential. A first low-voltage gate trigger silicon controlled rectifier cathode, a second low-voltage gate trigger silicon controlled rectifier anode and a third low-voltage gate trigger silicon controlled rectifier cathode are each coupled to a wire connected between a semiconductor pad and the semiconductor circuit. A current-limiting resistor is connected between the semiconductor pad and a linked terminal of trigger gates of the first low-voltage gate trigger silicon controlled rectifier, the second low-voltage gate trigger silicon controlled rectifier and the third low-voltage gate trigger silicon controlled rectifier.
REFERENCES:
patent: 4595941 (1986-06-01), Avery
patent: 5182220 (1993-01-01), Ker et al.
Chang Chun-Yen
Lee Chung-Yuan
Gaffin Jeffrey A.
Sherry Michael J.
United Microelectronics Corporation
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