Low voltage fully differential analog-to-digital converter

Details Low voltage fully differential analog-to-digital converter Low voltage fully differential analog-to-digital converter

2000-12-01

2002-04-09

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S159000

Reexamination Certificate

active

06369732

ABSTRACT:

BACKGROUND OF THE INVENTION
A. Field of the Invention
This present invention relates to an analog-to-digital converter and, in particular, to a low voltage fully differential analog-to-digital converter.
B. Description of the Related Art
FIG. 1
shows a schematic structure diagram of a conventional flash type analog-to-digital converter (hereinafter referred as ADC). The ADC
110
consists of an input stage branch
111
, a comparison stage branch
112
, and a decoding branch
113
. The comparison stage branch
112
has a plurality of comparators
1121
and each comparator
1121
is used to compare two voltages at two output terminals Vo
1
and Vo
2
of respective input cell
100
of the input stage branch
111
. And, the output of the comparator
1121
is logic
1
when Vo
1
is higher than Vo
2
while the output of the comparator
1121
is logic
0
when Vo
1
is lower than Vo
2
. The decoding branch
113
is to convert the signals from the comparators
1121
of the comparison stage branch
112
into binary digital signals.
FIG.
2
(A) shows a type of the input stage branch used in the ADC of
FIG. 1
disclosed in the invention of U.S. Pat. No. 5,175,550. The input stage branch
111
consists of a plurality of input cells
100
connected by cascade. Each input cell
100
includes a differential pre-amplifier
101
, two pieces of load bearing impedance
102
connected to two output terminals of the differential pre-amplifier
101
, and an averaging impedance branch
103
connected to two output terminals of every input cell
100
. By the use of the averaging impedance branch
103
the characteristic difference between every input cell
100
can be equalized. As shown in
FIG. 1
, the input terminal Vin
1
of the differential pre-amplifier
101
is connected to the analog input signals while the other input terminal Vin
2
of the differential pre-amplifier
101
is connected to a partial voltage point of a reference voltage provided by the progressive resistors branch
104
. The progressive resistors branch
104
consists of progressive resistors connected in a network between a terminal Vref_H providing a reference voltage and a terminal Vref_L providing a low potential such as ground. When the voltage of Vin
1
is higher than that of Vin
2
, the first output terminal Vo
1
of the differential pre-amplifier
101
is at high level while its second output terminal Vo
2
is at low level in order to send a differential signal to the comparator
1121
.
FIG.
2
(B) shows another type of input stage branch used in the ADC of
FIG. 1
disclosed in the invention of U.S. Pat. No. 5,835,048. The structure of an input cell
100
′ is similar to that of the input cell
100
in
FIG. 2
(A) except that a passive element of load bearing impedance
102
of input cell
100
has been replaced by an active element of a current source
102
′.
However, as shown in
FIG. 3
regarding the first type of input cell in
FIG. 2
(A), when a supplied voltage is+3.3V, an output voltage of the differential pre-amplifier is very close to the supplied voltage 3.3V because the load
102
is a passive element such as resistors. When a successive processing stage is an active element and a supplied voltage is 3.3V, an output voltage resulted from the supplied voltage will be over of the range of operational voltage of a regular active element. Therefore, the following elements, such as folding type or interpolation type comparators, connected to the input stage branch
111
from behind must be limited to be a passive load. Thus, the design of successive processing stage is restricted and consequently its gain is limited.
With regard to the second type of input cell in FIG.
2
(B), the common mode voltage output from a differential pre-amplifier can be lowered by means of a current source loading. However, because the current source is made of transistors, the range of input voltage of analog input signals will be limited due to the critical voltage V
TH
(about 1V) of transistors. And, such input cell can not operate under a condition of lower supplied voltage (such as 2.5V). In the mean time, a relatively higher capacitance of such input cell limits its responding speed. Furthermore, such design is relatively more complicated while occupying more area of chip because of the replacement of a loading impedance with a current source.
SUMMARY OF THE INVENTION
In view of the aforesaid disadvantages, one of objects of the present invention is to provide a low voltage fully differential analog-to-digital converter which can be operational under a condition of lower supplied voltage.
Another object of the present invention is to provide a low voltage fully differential analog-to-digital converter which can be operational within a range of higher frequency. And, a successive processing stage of an active element can be connected to an input stage of the low voltage fully differential analog-to-digital converter from behind.
A low voltage fully differential analog-to-digital converter according to the present invention consists of an input stage including a plurality of differential input cells for producing pre-output signals and successive processing stages for receiving pre-output signals from input stages. And, the low voltage fully differential analog-to-digital converter according to the present invention further consists of a decoder for receiving post-output signals from successive processing stages. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch.
The first differential pre-amplifier includes two transistors whose sources are connected together and connected with a low supplied voltage through a current source, and whose drains are respectively connected to first and second output terminals. The gates of these two transistors are respectively connected to a first input signal and a partial voltage point of a reference voltage branch. The second differential pre-amplifier includes two transistors whose sources are connected together and connected with a low supplied voltage through a current source, and whose drains are respectively connected to first and second output terminals. The gates of these two transistors are respectively connected to a second input signal and a partial voltage point of a reference voltage branch.
One end of the bias impedance is connected to a high supplied voltage while the other end of the bias impedance is connected to first and second output terminals through two respective pieces of load bearing impedance. Therefore, the offset of output voltages of first and second output terminals can be adjusted thereby. An averaging impedance branch consists of two sets of impedance that first set of impedance connects the second output terminal of the differential input cell and the first output terminal of an adjacent differential input cell. And, second set of impedance connects the other end of the bias impedance of the differential input cell and the other end of the bias impedance of an adjacent differential input cell.
The mentioned objects, various other objects, advantages, and features of the present invention will be more fully understood from the following detailed description of the preferred aspect of the invention when considered in connection with the accompanying drawings.


REFERENCES:
patent: 5175550 (1992-12-01), Kattmann et al.
patent: 5589831 (1996-12-01), Knee
patent: 5742248 (1998-04-01), Vorenkamp et al.
patent: 5835048 (1998-11-01), Bult
patent: 6014097 (2000-01-01), Brandt

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