Low voltage flash EEPROM memory cell with merge select transisto

Details Low voltage flash EEPROM memory cell with merge select transisto Low voltage flash EEPROM memory cell with merge select transisto

1993-10-12

1995-07-11

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

257316, 257317, 257320, 257321, 365900, G11C 700

Patent

active

054327407

ABSTRACT:
A EEPROM memory array (10) includes a plurality of memory cells (24) which are connected in a symmetric array between row lines (26) and Column Lines (28) and Virtual Ground Lines (29). Each of the memory cells includes a merged pass gate which is connected to a control gate. A non-stacked structure is utilized wherein a floating gate (42) is formed, having two portions that extend over an active region, a tunnel diode portion (44) and a control gate portion (46). The floating gate portion (44) is disposed over a thin tunnel oxide layer (47) to form a tunnel diode which allows Fowler-Nordheim tunneling to occur. The control gate portion (46) is disposed over a much thicker oxide layer such that tunneling does not occur. A control gate layer (50) is disposed over the floating gate (42) such that it overlaps the edges thereof and encloses the floating gate (42). On the one side of the floating gate (42), the control gate extends over the gate oxide layer in an extended portion (52) to form a pass gate structure. The pass gate structure is a merged structure formed in series with the floating gate cell. The merged pass gate has a controllable threshold that allows the floating gate cell to be overerased without causing unwanted conduction when the cell is unselected.

REFERENCES:
patent: 5033023 (1991-07-01), Hsia
patent: 5040147 (1991-08-01), Yoshizawa
patent: 5111270 (1992-05-01), Tzeng

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