Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-09-20
2003-04-22
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185140, C257S315000, C438S257000
Reexamination Certificate
active
06552931
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a voltage transfer device for use in a memory cell and, more specifically, to a low voltage floating gate non-volatile memory cell with improved data retention.
BACKGROUND OF THE INVENTION
With the reality of systems on a chip (SoC), large amounts of memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are required and presently embedded within Application-Specific Integrated Circuits (ASIC), logic, and processor chips. To keep yields reasonable, memory redundancy is highly desirable. One conventional approach used to achieve memory redundancy involved laser-link redundancy processes. However, a disadvantage of laser-link redundancy is that it requires large capital investment and is not well suited for low to medium volume ASIC due-to per code engineering efforts and setup costs. A more cost-effective method for controlling redundancy uses non-volatile switches, which employ single-poly programmable read only memory (PROM) cells to achieve low fabrication costs by only using one masking step in addition to those in the core complementary metal oxide semiconductor (CMOS) technology. Other applications for single-poly flash non-volatile memory cells are storage of secure or other identification codes and function switches, and storage of small amounts of data or code.
To minimize leakage of charge from the floating gate, the gate oxide in some PROM memory cells are typically thicker than in the core CMOS technology with which the memory is often associated. For example, the gate oxide thickness in memory cells may be as much as 10 nm thick, while the gate oxide thickness in the core CMOS technology may be about 5 nm thick. Due to the difference in the gate oxide thickness, the core CMOS devices typically have a threshold voltage (V
T
) of about 0.6 volts, while the memory cell devices have a V
T
of about 1.2 volts. The difference in these threshold voltages poses problems for the proper operation of the memory cell.
When reading a conventional non-volatile floating gate erased cell, the word-line voltage is typically first dropped across the gate oxide MOS capacitor (MC
1
) until the voltage across MC
1
reaches a typical threshold voltage of about 1.2 volts. The remainder of the word-line voltage swing raises the potential of the memory cells floating gate. With a word-line swing of 1.5 volts, the floating gate is only moved 0.3 volts, which is insufficient for proper operation of the memory cell. To make a typical erased cell conductive when raising the row, the floating gate must reach at least 1.35 volts, which is the threshold voltage plus about 0.15 volts of drive voltage. To do this, 1.05 volts of charge must have been placed on the floating gate by prior erasure. Due to the relatively large electric field across the oxide corresponding to this large amount of floating gate charge, the charge is likely to leak off the floating gate, destroying data retention. Furthermore, the signal margin associated with the small floating gate voltage swing (0.3 volts) is too small for reliable operation. If the cell loses as much as 150 mV of floating gate charge, or if there is 150 mV of power supply or word-line noise, the cell can read in error.
One memory cell provides a low-cost single-poly EEPROM cell. However, this cell is not compatible with the relatively low source/drain to tub breakdown voltages, nor the low power supply voltages common in today's low voltage CMOS technologies. More specifically, this particular device was configured to operate in older technologies having higher voltages of about 5 volts. Due to the higher voltages, there was enough voltage, after the threshold voltage drop across MC
1
, to operate the memory cell's switch. In addition, the core CMOS device gate oxides in these older technologies were thicker, so the threshold increase between the core CMOS technology and the EEPROM memory devices was smaller or nonexistant. Moreover, the lower junction breakdown voltage associated with these conventional devices in the newer technologies, prevents erasing with Fowler-Northam (FN) tunneling and limits the lowering of cell threshold when erasing with hot hole injection from band-to-band tunneling.
Accordingly, what is needed in the art is a low cost memory cell that does not experience data retention problems associated with prior art devices and that operates with low power supply voltages, high device thresholds, and low source/drain to tub breakdown voltage.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.
REFERENCES:
patent: 5686332 (1997-11-01), Hong
patent: 5780341 (1998-07-01), Ogura
patent: 6077716 (2000-06-01), Yoo
patent: 6151254 (2000-11-01), Kanamori
patent: 6157058 (2000-12-01), Ogura
McPartland Richard J.
Singh Ranbir
Agere Systems Inc.
Ho Hoai
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