Low voltage flash EEPROM C-cell using fowler-nordheim tunneling

Details Low voltage flash EEPROM C-cell using fowler-nordheim tunneling Low voltage flash EEPROM C-cell using fowler-nordheim tunneling

1995-05-25

1996-09-17

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518516, 36518533, 257316, G11C 1604

Patent

active

055575692

ABSTRACT:
A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage. To selectively erase one of the memory cells (24), the Column Line (28) associated with the programming side of the select memory cell transistor is connected to a positive medium voltage and the associated line (26) is connected to a positive Read voltage. The remaining Word Lines are connected to a negative Read voltage and the remaining Column Lines (28) are connected to a zero volt level.

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