Low voltage dual-modulus prescaler circuit using merged pseudo-d

Details Low voltage dual-modulus prescaler circuit using merged pseudo-d Low voltage dual-modulus prescaler circuit using merged pseudo-d

1998-09-30

2000-12-05

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

327115, 327117, H03K 2100

Patent

active

06157693&

ABSTRACT:
A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a master-slave flip-flop. An input clock signal having a frequency FN is supplied to the flip-flop of each circuit block, and an output clock signal having a frequency FN/2 or FN/3 is generated in response. A control signal supplied to the OR gate of the second circuit block determines whether the frequency will be divided by 2 or by 3. The circuit blocks generate differential output signals, and common-mode signals are generated for supply to the OR gate inputs by summing and dividing the differential output signals with high value resistors.

REFERENCES:
patent: 4606059 (1986-08-01), Oida
patent: 5195111 (1993-03-01), Adachi et al.
patent: 5590163 (1996-12-01), Dufour
patent: 5859890 (1999-01-01), Shurboff et al.
patent: 5948046 (1999-09-01), Hagberg
patent: 5987089 (1999-11-01), Hawkins, Jr.

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