Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-09-26
2003-07-08
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C326S083000
Reexamination Certificate
active
06590432
ABSTRACT:
BACKGROUND OF INVENTION
This invention relates to CMOS differential buffers, and more particularly to low-voltage differential-signaling (LVDS) output buffers.
High-speed signaling can be a key to increased performance for networks, computers, telecom, and other electronic systems. External signaling can often limit performance, such as when signals are driven from an integrated circuit (IC) to another IC. External signals often drive higher capacitive and resistive loads than do internal signals.
While full-swing signaling is still used internally in IC's, more recently off-chip signaling has employed limited-voltage swings. Rather than swing the output a full rail-to-rail voltage such as 3.3 volts, the outputs swing only 350 milli-volts (mV) or so.
Two output signals per bit of information are used, rather than just one output.
The two outputs are driven to opposite states, in what is known as differential signaling. When one output swings up 175 mV, the other swings down 175 mV. The two differential signals can be connected together by a resistor at the far end of a cable driven by the outputs to produce a voltage difference when current-switching output drivers are used.
Such low-voltage differential signaling (LVDS) techniques can speed data rates and reduce electro-magnetic interference (EMI), even when long cables are driven.
FIG. 1
is a schematic diagram of a basic low-voltage differential signaling (LVDS) output buffer. Current-steering buffer
10
receives differential inputs V+, V− and generates differential outputs DOP, DON. Input V+ is applied to the gates of n-channel transistors
22
,
36
, while input V− is applied to the gates of n-channel transistors
32
,
26
.
When V+ rises and V− falls in voltage, transistors
22
,
36
are turned on more strongly while transistors
32
,
26
are turned off strongly. This pulls the voltage of DON lower, and DOP higher.
Current-source p-channel transistor
28
acts as a current source controlled by its gate bias, PBIAS. Likewise, current-sink n-channel transistor
38
is controlled by its gate bias, NBIAS, and sinks about 3.5 mA in one embodiment. Source resistor
24
can be placed in series with current-source p-channel transistor
28
.
When full-swing voltages are input for V+, V−, the full 3.5 mA of current is switched to either DOP or DON. For example, when Vcc is 3.3 volts, and V+ is driven high to 3.3 volts while V− is driven low to ground, n-channel transistors
32
,
26
turn off, while n-channel transistors
22
,
36
are on strongly. All the current from current-source p-channel transistor
28
flows through n-channel transistor
32
to output DOP, while n-channel transistor
36
sinks current from DON through current-sink n-channel transistor
38
.
An external load resistor (not shown) is typically connected between DOP, DON at the far end of a cable driven by buffer
10
. This load resistor produces a voltage between DOP, DON. As buffer
10
switches current among DOP, DON, the voltage on the load resistor varies and can be sensed by a differential sense amplifier or input on a receiver. For example, a 100-ohm load resistor generates a 0.35-volt IR drop when 3.5 mA of current flows from DON to DOP.
FIGS. 2A-C
are waveforms illustrating operation of the LVDS buffer of FIG.
1
. In
FIG. 2A
, an upstream input VIN switches from low-to-high and later back from high-to-low. This input VIN is converted to differential input signal V+, V− by standard logic to generate V+, V−. These are full-swing differential inputs, as shown in FIG.
2
B.
FIG. 2C
shows the differential outputs DOP, DON produced by buffer
10
of
FIG. 1
, when the differential inputs V+, V− of
FIG. 2B
are applied. The vertical (voltage) scale is enlarged in
FIG. 2C
, since VOH and VOL typically differ by only a few hundred mV, such as 350 mV (0.35 volt).
When differential inputs V+. V− switch, current is switched among the DOP, DON outputs, causing a switching of outputs DOP, DON around the common-mode voltage VOS. The voltage difference, VOD, generated across the load resistor is the resistance multiplied by the current switched, I*R. For a 100-ohm resistor and a 3.5-mA current, VOD is 350 mV.
The switching waveform of
FIG. 2C
is known as an eye pattern, since the opening between DOP and DON has an appearance similar to the shape of a human eye. The height of the eye opening is voltage difference VOD. When an actual circuit that drives a real cable is viewed using an oscilloscope or test analyzer, the waveforms of many cycles are superimposed on one another. The lines for DOP and DON then may appear fuzzy with a larger thickness. Distortions can occur, further reducing the opening of the eye pattern due to jitter and noise of the cable environment.
At very high frequencies, such as about 0.5-GigaHz, the height of the eye (VOD) can decrease significantly. When DOP is driven high at these high frequencies, it is kept lower in voltage than at low frequencies due to a parasitic capacitance.
Coupling between V− and DOP occurs across the drain-to-gate parasitic capacitance of n-channel transistor
26
. As V− falls in voltage, the rise in DOP is reduced by capacitive coupling across this parasitic gate-to-drain and drain to ground capacitor. This parasitic capacitor effect is more pronounced at higher frequencies. This limits operation at higher frequencies.
The eye pattern can be improved by using pre-emphasis techniques. When the output is first switched, a boosted current is used to initially increase the voltage difference. Then the current boost ends, and the voltage difference decreased to the normal value. The height of the eye is thus increased at the beginning (left side) of the eye when pre-emphasis is added.
An increased voltage difference at the beginning of the eye pattern can improve performance, since any distortions can be compensated by the larger voltage difference. At high frequencies when the parasitic capacitance reduces the voltage difference, pre-emphasis compensates by increasing the voltage difference.
Current-Boost Stage Adds Pre-emphasis—
FIG. 3
FIG. 3
is a schematic of a prior-art LVDS output buffer with a current-boost stage for pre-emphasis. See U.S. Pat. No. 6,288,581 by Wong and assigned to Pericom Semiconductor Corp. of San Jose, Calif. Primary buffer
11
steers current to outputs VOP, VON using transistors
22
,
26
that receive V+, and transistors
32
,
36
that receive V−.
Boost stage
20
is similar to primary buffer
11
, except that a smaller current is switched. Current is switched in a similar manner, with input V+ applied to the gates of p-channel transistor
42
and n-channel transistor
46
, while V− is applied to the gates of p-channel transistor
52
and n-channel transistor
56
.
Enable signal ENA is kept high when output signals VOP, VON are driven, so n-channel transistors
44
,
54
in boost stage
20
remain on, as do n-channel transistors
25
,
34
in primary-stage buffer
11
.
Link Transistors Between Stages Slow Boost N-channel link transistors
60
,
62
connect the outputs of the two stages
11
,
20
. Link transistor
60
allows the current from boost stage
20
to flow to output VOP, while link transistor
62
allows the current from boost stage
20
to flow to output VON.
Primary stage buffer
11
is always connected to outputs VOP, VON, while boost stage
20
is connected only when link transistors
60
,
62
are enabled.
The gates of link transistors
60
,
62
are driven by boost signal PREX. When boost signal PREX is high, the current from boost stage
20
is added to the current from primary-stage buffer
11
, increasing the output current. When boost signal PREX is low, only primary-stage buffer
11
drives the outputs.
Boost signal PREX is timed to increase current during and immediately after switching, but to return to normal current levels after a time delay. This timing provides a pre-emphasis period, when boost signal PREX is active. Dur
Wu Ke
Zhang Michael Y.
Auvinen Stuart T.
Pericom Semiconductor Corp.
Wells Kenneth B.
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