Amplifiers – With semiconductor amplifying device – Including protection means
Reexamination Certificate
2000-09-29
2002-11-19
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including protection means
C327S309000
Reexamination Certificate
active
06483386
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing differential amplifiers generally and, more particularly, to a method and/or architecture for implementing a low voltage differential amplifier with high voltage protection.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) can be required to operate with secondary devices that can have a variety of supply voltages. If the IC is implemented using low voltage, thin oxide devices, but needs to operate with devices that use higher voltages, some sort of protection needs to be provided for the low voltage devices.
FIG. 1
illustrates a conventional circuit
10
that uses thick oxide devices for high voltage protection. Such conventional approaches use high voltage devices HV
1
, HV
2
, HV
3
and HV
4
to implement an input differential amplifier.
Such an approach has the disadvantage of a reduced input common mode range due to a high threshold voltage Vt of the thick oxide devices HV
1
, HV
2
, HV
3
and HV
4
. Also, such an approach requires a larger silicon area to implement and has slower performance. The high voltage devices HV
1
, HV
2
, HV
3
and HV
4
are larger, which impacts the size and the parasitic capacitance of the circuit
10
.
FIG. 2
illustrates a conventional circuit
30
implementing high voltage complementary switches HV
1
and HV
2
(each comprising a p-channel and an n-channel device) to protect the input devices LV
1
and LV
2
of the low voltage input differential amplifier
32
. The circuit
30
has the disadvantage of implementing a combination of high voltage thresholds and a low voltage gate bias, which causes an input voltage region in which signals can not be passed to the low voltage amplifier
32
. This region is referred to as the dead zone, as shown in
FIG. 3
, where Vin is an input voltage. For example, if the n-channel device threshold voltage Vtn is 1.0V, the p-channel device threshold voltage Vtp is −1.0V, and the control voltages LV
13
COMP
13
EN and LV
13
COMP
13
ENb are 1.8V and 0.0V respectively, neither device of the complementary switches HV
1
and HV
2
will be turned on when the input level is between 0.8V and 1V. The dead zone region will be exaggerated as the control voltage LV
13
COMP
13
EN is reduced.
Both the circuit
10
and the circuit
30
do not meet the speed objective for the input paths of modern integrated circuits. Also, the circuit
30
fails to pass (or propagate) input levels residing within the dead zone, which is undesirable.
It would be desirable to implement a low voltage differential amplifier with high voltage protection that does not have a dead zone and does not sacrifice other performance specifications, such as speed, die size, input common mode range, etc.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a native device coupled to an input of an amplifier. The native device is configured to provide high voltage protection in response to an enable signal.
The objects, features and advantages of the present invention include implementing a low voltage differential amplifier that may (i) implement fast signal propagation through the differential amplifier; (ii) implement a simple high voltage protection scheme without requiring a voltage pump or voltage reference circuit; (iii) avoid input level dead zone regions that may be associated with conventional approaches; and/or (iv) allow the differential amplifier to be implemented with low voltage devices, which may yield a wide input common mode range and lower parasitic capacitance.
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patent: 4288804 (1981-09-01), Kikuchi et al.
patent: 4943738 (1990-07-01), Hoshi
patent: 5349305 (1994-09-01), Hsiao et al.
patent: 5412348 (1995-05-01), Kasha et al.
patent: 5440162 (1995-08-01), Worley et al.
patent: 5732015 (1998-03-01), Kazerpounian et al.
patent: 5850365 (1998-12-01), Reese et al.
patent: 5949710 (1999-09-01), Pass et al.
patent: 6175952 (2001-01-01), Patel et al.
patent: 6252422 (2001-06-01), Patel et al.
Cress Daniel E.
Hunt Jeffery Scott
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nguyen Khanh Van
Pascal Robert
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